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news/2014/05/06/open-source-network-tester-release-1-0-0.html create mode 100644 news/2014/07/04/OSNT-1-5-0.html create mode 100644 news/2014/07/23/NetFPGA-publication-list.html create mode 100644 news/2014/07/30/NetFPGA-10G-Release-5-0-4.html create mode 100644 news/2014/10/13/OSNT-release-2-0-0.html create mode 100644 news/2014/10/15/Announcing-NetFPGA-SUME.html create mode 100644 news/2014/10/21/NetFPGA-10G-Release-5-0-5.html create mode 100644 news/2014/12/22/NetFPGA-Newsletter-December-2014.html create mode 100644 news/2015/01/13/NetFPGA-10G-Release-5-0-6.html create mode 100644 news/2015/02/28/OSNT-2-1-0.html create mode 100644 news/2015/04/08/NetFPGA-10G-Release-5-0-7.html create mode 100644 news/2015/05/26/CML-Release-5-0-5.html create mode 100644 news/2015/06/15/Newsletter.html create mode 100644 news/2015/10/12/NetFPGA-SUME-Release-1-0-0.html create mode 100644 news/2015/12/16/NetFPGA-SUME-1-1-0.html create mode 100644 news/2016/01/29/NetFPGA-SUME-Release1-2-0.html create mode 100644 news/2016/02/01/NetFPGA-Newsletter-February-2016.html create mode 100644 news/2016/05/24/NetFPGA-SUME-Release-1-3-0.html create mode 100644 news/2016/10/04/NetFPGA-SUME-Release-1-4-0.html create mode 100644 news/2016/11/16/NetFPGA-Development-Challenge-April-2017.html create mode 100644 news/2016/12/13/NetFPGA-SUME-Release-1-5-0.html create mode 100644 news/2017/03/21/NetFPGA-Design-Challenge-April-2017.html create mode 100644 news/2017/03/22/Meet-NetFPGA.html create mode 100644 news/2017/03/22/OSNT-on-SUME-now-available.html create mode 100644 news/2017/07/13/NetFPGA-SUME-Release-1-6-0.html create mode 100644 news/2017/08/03/NetFPGA-SUME-Release-1-6-1.html create mode 100644 news/2017/10/13/NetFPGA-SUME-Release-1-7-0.html create mode 100644 news/2017/12/14/NetFPGA-SUME-Release-1-7-1.html create mode 100644 news/2018/01/30/NetFPGA-SUME-Release-1-8-0.html create mode 100644 news/2019/04/01/NetFPGA-SUME-Release-1-9-0.html create mode 100644 news/2019/04/02/NetFPGA-project-wins-SOSR-System-Award.html create mode 100644 news/2020/10/02/NetFPGA-SUME-Release.html create mode 100644 news/2021/09/24/NetFPGA-PLUS-Release-1.0.html create mode 100644 why-NetFPGA.html diff --git a/.nojekyll b/.nojekyll new file mode 100644 index 0000000..e69de29 diff --git a/10G-reg-form.html b/10G-reg-form.html new file mode 100644 index 0000000..253a9af --- /dev/null +++ b/10G-reg-form.html @@ -0,0 +1,126 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

NetFPGA 10G Beta program Registration

+
+
+

+ A more comprehensive Getting Started page will be available once you have registered.
+ The code base is available as a git repository hosted on GitHub.
+ To access the release, please first fill out this registration form with your GitHub username. The rest of the information helps us learn a little bit about you, and keep in touch with you about NetFPGA updates and news. +



+ + +
+
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+ + + + + + + + + + + diff --git a/2021/07/15/NetFPGA.html b/2021/07/15/NetFPGA.html new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/2021/07/15/NetFPGA.html @@ -0,0 +1 @@ + diff --git a/2021/07/16/IIsy.html b/2021/07/16/IIsy.html new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/2021/07/16/IIsy.html @@ -0,0 +1 @@ + diff --git a/2021/07/16/In-Network-Computing-on-Demand.html b/2021/07/16/In-Network-Computing-on-Demand.html new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/2021/07/16/In-Network-Computing-on-Demand.html @@ -0,0 +1 @@ + diff --git a/2021/07/16/MTPSA.html b/2021/07/16/MTPSA.html new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/2021/07/16/MTPSA.html @@ -0,0 +1 @@ + diff --git a/2021/07/16/OSNT.html b/2021/07/16/OSNT.html new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/2021/07/16/OSNT.html @@ -0,0 +1 @@ + diff --git a/2021/07/16/P4DNS.html b/2021/07/16/P4DNS.html new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/2021/07/16/P4DNS.html @@ -0,0 +1 @@ + diff --git a/2021/07/16/PTA.html b/2021/07/16/PTA.html new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/2021/07/16/PTA.html @@ -0,0 +1 @@ + diff --git a/About.html b/About.html new file mode 100644 index 0000000..90ad708 --- /dev/null +++ b/About.html @@ -0,0 +1,319 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
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+
+ + +
+
+
+

About NetFPGA

+

The NetFPGA is an open source hardware and software platform designed for research and teaching. Currently there are two supported platforms: NetFPGA-SUME and NetFPGA-PLUS and three old platforms: NetFPGA-1G-CML, NetFPGA-10G and the NetFPGA-1G. These platforms allow researchers, and students to build prototypes of high-speed, hardware-accelerated networking systems. As of 2019 the NetFPGA platforms have been used in over 400 academic papers. Our platforms are open-source and the hardware is made available at low cost through donations of gifts and silicon chips by sponsors of the NetFPGA project.

+

Tutorials have been held worldwide to teach new users with hands-on experience using the NetFPGA. There are now over 150 groups around the globe that use the NetFPGA.

+ +

Supporters of the NetFPGA project

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+ Stanford University Logo +
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+ University of Cambridge Logo +
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+ University of Oxford Logo +
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+ National Science Foundation Logo +
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+ EPSRC Logo +
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+ Xilinx Logo +
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Past Supporters

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+ Agilent Logo +
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+ Algo-logic Logo +
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+ Broadcom Logo +
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+ Cisco Logo +
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+ CML Logo +
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+ Cypress Logo +
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+ Digilent Logo +
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+ Solarflare Logo +
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+ Synplicity Logo +
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Past hosts of hands-on tutorials

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+ Beijing Jiaotong University +
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+ BRNO University of Technology +
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+ University of Delaware +
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+ Forth Institute of Computer Science +
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+ Indiana University +
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+ IETF +
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+ Indian Institute of Science +
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+ University of Kentucky +
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+ University of Melbourne +
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+ Ofelia +
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+ Poznen University of Technology +
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+ Pursuit +
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+ Seoul National University +
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+ ACM SIGMETRICS +
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+ Technische Universität Berlin +
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+ Tsinghua University +
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+ UNSW +
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+ + + + + + + + + + + diff --git a/CML-reg-form.html b/CML-reg-form.html new file mode 100644 index 0000000..a007620 --- /dev/null +++ b/CML-reg-form.html @@ -0,0 +1,121 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

NetFPGA 1G CML Registration

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+ + + + + + + + + + + diff --git a/CNAME b/CNAME new file mode 100644 index 0000000..1de72a1 --- /dev/null +++ b/CNAME @@ -0,0 +1 @@ +netfpga.org diff --git a/NetFPGA-10G.html b/NetFPGA-10G.html new file mode 100644 index 0000000..0317f06 --- /dev/null +++ b/NetFPGA-10G.html @@ -0,0 +1,331 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

NetFPGA 10G

+
+
+
+ +
+
+

The NetFPGA-10G is an FPGA-based PCI Express board with 10-Gigabit SFP+ interface, a x8 gen1 PCIe adapter card incorporating Xilinx’s Virtex-5 TX240TFPGA. It is ideal for the high bandwidth applications.

+

Features list:

+
    +
  • Field Programmable Gate Array (FPGA) Logic
    • +
  • 10-Gigabit Ethernet networking ports
      +
    • 4 SFP+ connectors
      • +
    • Connected to the FPGA through four Broadcom’s AEL2005 PHY devices
      • +
    • Supports both 10-Gigabit and 1-Gigabit modes
      • +
    • +
  • Quad Data Rate Static Random Access Memory (QDRII SRAM)
      +
    • Suitable for storing and forwarding table data
      • +
    • 300MHz Quad data rate (1.2 Giga transactions every second), synchronous with the logic
      • +
    • Three parallel banks of 72 MBit QDRII+ memories
      • +
    • Total capacity: 27 MBytes
      • +
    • Cypress: CY7C1515KV18
      • +
    • +
  • Reduced Latency Random Access Memory (RLDRAM II)
      +
    • Suitable for packet buffering
      • +
    • Four x36 RLDRAMII on-board device
      • +
    • 400MHz clock (800MT/s)
      • +
    • 115.2 Gbps peak memory throughput
      • +
    • Total Capacity: 288MByte
      • +
    • Micron: MT49H16M36HT-25
      • +
    • +
  • PCI Express Gen. 1
      +
    • First generation PCI Express interface, 2.5Gbps/lane
      • +
    • 8 lanes (x8)
      • +
    • Hard IP
      • +
    • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
      • +
    • x4 Gen.2 PCI Express can be used as a soft core
      • +
    • +
  • Storage
      +
    • Two FLASH devices
      • +
    • Total Capacity: 256Mb
      • +
    • +
  • Expansion Interfaces
      +
    • Two SAMTEC QTH connectors
      • +
    • Allowing to connect additional 20 RocketIO GTX transceivers
      • +
    • +
  • Additional Features
      +
    • DB9 (RS232) Connector
      • +
    • User LEDs & Push Buttons
      • +
    • +
  • Standard PCIe Form Factor
      +
    • Standard PCIe card
      • +
    • 3/4 length, full height
      • +
    • +
  • Flexible, Open-source code
    • +
+
+
+
+
+
+ +
+

To see the NetFPGA-10G repository and Wiki you will need to register.

+

Reference Projects

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TitleOrganisationDocumentation
Production TestStanford UniversityWiki
RLDRAM TestXilinxWiki
10G Ethernet Interface Loopback TestStanford University / University of CambridgeWiki
1G Ethernet Interface Loopback TestStanford University / University of CambridgeWiki
Reference NIC 10GStanford University / University of CambridgeWiki
Reference NIC 1GStanford University / University of CambridgeWiki
Flash ConfigurationUniversity of CambridgeWiki
Learning CAM SwitchUniversity of Pisa / University of CambridgeWiki
+

Contributed Projects

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TitleOrganisationDocumentation
NetFPGA-1G Ported Switch 10GUniversity of Pisa / University of CambridgeWiki
NetFPGA-1G Ported NIC 1GUniversity of Pisa / University of CambridgeWiki
NICStanford University / University of CambridgeWiki
OpenFlow SwitchStanford UniversityWiki
NIC (SRAM)Stanford University / University of CambridgeWiki
Simple 10G SwitchXilinxWiki
NetFlow simple 10G BramUniversidad Autónoma de MadridWiki
FlashUniversity of CambridgeWiki
+
+
+
+
+
+ +
+
+

Where can I buy a NetFPGA 10G Platform?

+ +

It seems that my board is broken, what should I do?

+ +

What if I have Hardware problems with my board?

+ +

What if I have Software problems with my board?

+ +

You can exchange your ideas and questions with the NetFPGA 10G community here.

+

How can I get involved with the NetFPGA project?

+ +

How can I obtain the gateware and software package?

+ +
+

Once you have used the NetFPGA, we hope that you will contribute to the project.

+
+

You can find our Wiki here.

+
+
+
+
+ +
+
+ +
+ + + + + + + + + + + diff --git a/NetFPGA-1G.html b/NetFPGA-1G.html new file mode 100644 index 0000000..9211c46 --- /dev/null +++ b/NetFPGA-1G.html @@ -0,0 +1,501 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

NetFPGA 1G

+
+
+
+ +
+
+

The NetFPGA is the low-cost reconfigurable hardware platform optimized for high-speed networking. The NetFPGA includes the all fo the logic resources, memory, and Gigabit Ethernet interfaces necessary to build a complete switch, router, and/or security device. Because the entire datapath is implemented in hardware, the system can support back-to-back packets at full Gigabit line rates and has a processing latency measured in only a few clock cycles.

+
    +
  • Field Programmable Gate Array (FPGA) Logic
      +
    • Xilinx Virtex-II Pro 50
      • +
    • 53,136 logic cells
      • +
    • 4,176 Kbit block RAM
      • +
    • up to 738 Kbit distributed RAM
      • +
    • 2 x PowerPC cores
      • +
    • Fully programmable by the user
      • +
    • +
  • Gigabit Ethernet networking ports
      +
    • Connector block on left of PCB interfaces to 4 external RJ45 plugs
      • +
    • Interfaces with standard Cat5E or Cat6 copper network cables using Broadcom PHY
      • +
    • Wire-speed processing on all ports at all time using FPGA logic
        +
      • 1 Gbits * 2 (bi-directional) * 4 (ports) = 8 Gbps throughput
        • +
      • +
    • +
  • Static Random Access Memory (SRAM)
      +
    • Suitable for storing forwarding table data
      • +
    • Zero-bus turnaround (ZBT), synchronous with the logic
      • +
    • Two parallel banks of 18 MBit (2.25 MByte) ZBT memories
      • +
    • Total capacity: 4.5 MBytes
      • +
    • Cypress: CY7C1370D-167AXC
      • +
    • +
  • Double-Date Rate Random Access Memory (DDR2 DRAM)
      +
    • 400 MHz Asynchronous clock
      • +
    • Suitable for packet buffering
      • +
    • 25.6 Gbps peak memory throughput
      • +
    • Total capacity: 64 MBytes
      • +
    • Micron: MT47H16M16BG-5E
      • +
    • +
  • Multi-gigabit I/O
      +
    • Two SATA-style connectors to Multi-Gigabit I/O (MGIO) on right-side of PCB
      • +
    • Allows multiple NetFPGAs within a PC to be chained together
      • +
    • +
  • Standard PCI Form Factor
      +
    • Standard PCI card
      • +
    • Can be used in a PCI-X slot
      • +
    • Enables fast reconfiguration of the FPGA over PCI bus without using JTAG cable
      • +
    • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
      • +
    • +
  • Hardware Debugging ports
      +
    • JTAG cable connector can be used to run Xilinx ChipScope Pro
      • +
    • +
  • Flexible, Open-source code
      +
    • BSD-style open-source reference router available from the NetFPGA.org website. Download it, use it, keep it, give back to the community if you choose.
      • +
    • +
+
+
+
+
+
+ +
+

Projects

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TitleOrganisationDocumentation
IPv4 Reference RouterStanford UniversityWiki
Quad-Port Gigabit NICStanford UniversityWiki
Ethernet SwitchStanford UniversityWiki
Buffer Monitoring SystemStanford UniversityWiki
Hardware-Accelerated Linux RouterStanford UniversityWiki
DRAM-RouterStanford UniversityWiki
DRAM-Queue TestStanford UniversityWiki
Packet GeneratorStanford UniversityWiki
OpenFlow SwitchStanford UniversityWiki
NetFlow ProbeBrno UniversityWiki
AirFPGAStanford UniversityWiki
Fast Reroute & Multipath RouterStanford UniversityWiki
NetThreadsUniversity of TorontoWiki
NetThreads-REUniversity of TorontoWiki
NetTMUniversity of TorontoWiki
Precise Traffic GeneratorUniversity of TorontoWiki
URL ExtractionUniv. of New South WalesWiki
zFilter Sprouter (Pub/Sub)EricssonWiki
Windows DriverMicrosoft ResearchWiki
REDStanford UniversityWiki
Open Network LabWashington UniversityWiki
DFAUMass LowellWiki
G/PaXXilinxWiki
RCP RouterStanford UniversityWiki
Deficit Round Robin (DRR)Stanford UniversityWiki
OpenFlow-MPLS SwitchEricssonWiki
PTP-enabled RouterStanford UniversityWiki
Vlan Tag HandlerStanford UniversityWiki
Port AggregatorStanford UniversityWiki
IP Lookup w/Blooming TreeUniversity of PisaWiki
KOREN TestbedChungnam-KoreaWiki
Virtual Data PlaneGeorgia TechWiki
Deficit Round Robin (DRR) Input ArbiterUniversidade Federal do Rio Grande do Sul (Brazil)Wiki
Counter BraidsStanford (Lu, Jianying)Wiki
Ethernet Switch with Real-time supportUniversity of Waterloo and Universidad de ConcepcionWiki
End-to-End Ethernet AuthorizationEuskal Herriko UnibertsitatekoWiki
Ultra-high Speed Congestion-controlUniversity of North CarolinaWiki
Promiscuous Reference RouterUniversity of CataniaWiki
BORPH (Operating System)University of Hong Kong / University of Cape TownWiki
Traffic MonitorUniversity of CataniaWiki
Latency Measurement ModuleAlgo-Logic SystemsWiki
NetFPGA Logic AnalyzerUSC/ISIWiki
Bounded Jitter PolicyUniversity of TorontoWiki
Traffic ClassifierUniversity of TorontoWiki
Network IO FairnessGeorgia TechWiki
Tunneling OpenFlow Switch with ICMPStanford UniversityWiki
zFormation PSrouter (Pub/Sub)EricssonWiki
High Performance Packet ClassifierUniversity of PisaWiki
Flexible RouterUniversity of CataniaWiki
Monitoring SystemUniversity of Pisa / University of CambridgeWiki
Deficit Round Robin Router BackplaneCairo UniversityWiki
NetCoding Project Transmit Node?Download
Router Buffer AdaptationUniversity of New South WalesWiki
+
+
+
+
+
+ +
+
+

Where can I buy a NetFPGA 1G platform

+ +

It seems that my board is broken, what should I do?

+ +

What if I have Hardware problems with my boards?

+ +

What if I have Software problems with my board?

+
    +
  • Register to the NetFPGA Forums.
    • +
+

You can exchange your ideas and questions with the NetFPGA community here.

+

How can I get involved with the NetFPGA project?

+ +

How can I obtain the gateware and software package?

+ +
+

Once you have used the NetFPGA, we hope that you will contribute to the project.

+
+

You can find our Wiki here.

+
+
+
+
+ +
+
+ +
+ + + + + + + + + + + diff --git a/NetFPGA-CML.html b/NetFPGA-CML.html new file mode 100644 index 0000000..fe0db5b --- /dev/null +++ b/NetFPGA-CML.html @@ -0,0 +1,271 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

NetFPGA CML

+
+
+
+ +
+
+

The NetFPGA-1G-CML is an FPGA-based PCI Express board with Gigabit Ethernet I/O, an x4 gen2 PCIe adapter card incorporating Xilinx’s Kintex-7 325T FPGA. It is ideal for the development of highly complex, low bandwidth applications.

+

Features list:

+
    +
  • Field Programmable Gate Array (FPGA) Logic
      +
    • Xilinx Kintex-7 325T
      • +
    • 326,080 logic cells
      • +
    • 16,020 Kbit block RAM
      • +
    • up to 4,000 Kbit distributed RAM
      • +
    • Fully programmable by the user
      • +
    • +
  • Gigabit Ethernet networking ports
      +
    • Four 10/100/1000 Ethernet PHYs with RGMII
      • +
    • Wire-speed processing on all ports at all time using FPGA logic
      • +
    • +
  • Quad Data Rate Static Random Access Memory (QDRII+ SRAM)
      +
    • Suitable for storing and forwarding table data
      • +
    • 450MHz Quad data rate (1.8 Giga transactions every second), synchronous with the logic
      • +
    • 36 MBit (4.5 MBytes) QDRII+ memory
      • +
    • Cypress: CY7C2263KV18
      • +
    • +
  • Double-Date Rate Random Access Memory (DDR3 DRAM)
      +
    • Suitable for packet buffering
      • +
    • x8 DDR3 on-board device
      • +
    • 800MHz clock (1600MT/s)
      • +
    • 12.8 Gbps peak memory throughput
      • +
    • Capacity: 512MByte
      • +
    • Micron: MT41K512M8
      • +
    • +
  • PCI Express Gen. 2
      +
    • Second generation PCI Express interface, 5Gbps/lane
      • +
    • 4 lanes (x4)
      • +
    • Hard IP
      • +
    • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
      • +
    • +
  • Storage
      +
    • SD-card slot
      • +
    • 1Gbit FLASH
      • +
    • +
  • Expansion Interfaces
      +
    • Fully compliant VITA-57 FMC HPC connector, including 4 high-speed serial links (GTX)
      • +
    • Two Digilent PMOD expansion connectors
      • +
    • +
  • Additional Features
      +
    • 32-bit PIC microcontroller
      • +
    • USB microcontroller
      • +
    • Real Time clock
      • +
    • Crypto-authentication chip
      • +
    • User LEDs & Push Buttons
      • +
    • +
  • Standard PCIe Form Factor
      +
    • Standard PCIe card
      • +
    • 3/4 length, full height
      • +
    • +
  • Flexible, Open-source code
    • +
+
+
+
+
+
+ +
+

To see the NetFPGA-1G-CML repository and Wiki you will need to register.

+

Reference Projects

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TitleOrganisationDocumentation
Ethernet Interface Loopback TestCML / University of CambridgeWiki
Reference NICCML / University of CambridgeWiki
Reference FlashCML / University of CambridgeWiki
Learning CAM SwitchCML / University of CambridgeWiki
Learning Switch (Lite)CML / University of CambridgeWiki
Reference RouterCML / University of CambridgeWiki
+
+
+
+
+
+ +
+
+

Where can I buy a NetFPGA 1G CML Platform?

+ +

It seems that my board is broken, what should I do?

+ +

What if I have Hardware problems with my board?

+ +

What if I have Software problems with my board?

+ +

You can exchange your ideas and questions with the NetFPGA CML community here.

+

How can I get involved with the NetFPGA project?

+ +

How can I obtain the gateware and software package?

+
  • Registration
    • +
  • NetFPGA-1G-CML license
    • +
    +

    Once you have used the NetFPGA, we hope that you will contribute to the project.

    +
    +

    You can find our Wiki here.

    +
    +
    +
    +
    + +
    +
    + +
    + + + + + + + + + + + diff --git a/NetFPGA-PLUS.html b/NetFPGA-PLUS.html new file mode 100644 index 0000000..b67d4a1 --- /dev/null +++ b/NetFPGA-PLUS.html @@ -0,0 +1,259 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA PLUS

    +
    +
    +
    + +
    +
    +

    The NetFPGA PLUS is a code base built for the Xilinx Alveo Data Center Accelerator Card based upon Xilinx Virtex Ultrascale+ FPGAs. The code base currently operates on the U200, U250 and U280 as well as the discontinued VCU1525 Acceleration Development Kit.

    +
    +

    A typical Alveo board is an FPGA-based PCI Express board with I/O capabilities for 10 and 100 Gbps operation, an x16 gen3 PCIe adapter card. It can be used as NIC, multiport switch, firewall, test/mesaurement environment, and more.

    +

    Full feature lists are available at the Xilinx Alveo website.

    +

    Example feaures (e.g., U250)

    +
      +
    • Field Programmable Gate Array
      • +
        +
      • Xilinx Ultrascale+ VCU250
        • +
      • 1,728K logic cells
        • +
      • 57MB block RAM
        • +
      • Fully programmable by the user
        • +
      +
    • 100-Gigabit Ethernet networking ports
      • +
        +
      • Connector bloack on left of PCB interfaces to 2 QSFP+ ports
        • +
      • Directly connected to the FPGA.
        • +
      • Wire-speed processing on all ports at all time using FPGA logic.
        • +
      +
    • Double-Data Rate Random Access Memory (DDR4 DRAM)
      • +
        +
      • 4x 16GB 72b DIMM DDR4
        • +
      • 933MHz clock (2400MT/s)
        • +
      • 77 GB/s peak memory throughput
        • +
      +
    • PCI Express Gen. 3
      • +
        +
      • Third generation PCI Express interface, 8Gbps/lane
        • +
      • 16 lanes (x16)
        • +
      • Hard IP
        • +
      • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
        • +
      +
    • Storage
      • +
        +
      • FLASH devices
        • +
      +
    • Standard PCIe Form Factor
      • +
        +
      • Standard PCIe card
        • +
      • 3/4 or Full length, full height
        • +
      +
    • Flexible, Open-source code
      • +
    +
    +
    +
    +
    +
    + +
    +

    Reference Projects

    + + + + + + + + + + + + + + + + + + + + + + + + + + +
    TitleOrganisationDocumentation
    Reference SwitchUniversity of CambridgeWiki
    Reference Switch LiteUniversity of CambridgeWiki
    Reference NICUniversity of CambridgeWiki
    Reference RouterUniversity of CambridgeWiki
    + +
    +
    +
    +
    +
    + +
    + +
    +

    Where can I buy a NetFPGA PLUS Platform?

    +
      +
    • NetFPGA PLUS is initended to run on a range of the Xilinx +Vivado Ultra+ so contact your Xilinx reseller.
      • +
    +

    It seems that my board is broken, what should I do?

    +
      +
    • The Xilinx / Alveo boards have support for hardware repair +andreplacement, contact your Xilinx seller.
      • +
    +

    What if I have Hardware problems with my board?

    +
      +
    • The Xilinx / Alveo boards are no longer bespoke; like any +commodity, consult the people who sold it to you.
      • +
    +

    What if I have Software problems with my board?

    +
      +
    • If the software problem is exclusively related to the +NetFPGA-PLUS codebase, then use the bug-tracking mechaisms on the GitHub +platform associated with the NetFPGA-PLUS repository.
      • +
    +

    How can I get involved with the NetFPGA project?

    +
      +
    • We have a number of mailing lists, unlike SUME, and other previous +boards we no longer require explcit registation. Standby for detals +once we have our new procedures for contribution in place. In the firsst +insntance the issues tracker associated with the PLUS repository is a +great place to start.
      • +
    • Become a fan on Facebook.
      • +
    • Become a fan on twitter.
      • +
    +

    How can I obtain the gateware and software package?

    +
      +
    • Check out the repository link in the Resources tab.
      • +
    +

    Once you have used the NetFPGA, we hope that you will contribute to the project.

    +

    You can find our Wiki here.

    + + +
    +
    +
    +
    + +
    +
    + +
    + + + + + + + + + + + diff --git a/NetFPGA-SUME.html b/NetFPGA-SUME.html new file mode 100644 index 0000000..1aa0b20 --- /dev/null +++ b/NetFPGA-SUME.html @@ -0,0 +1,272 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA SUME

    +
    +
    +
    + +
    +
    +

    The NetFPGA SUME is an FPGA-based PCI Express board with I/O capabilities for 10 and 100 Gbps operation, an x8 gen3 PCIe adapter card incorporating Xilinx’s Virtex-7 690T FPGA. It can be used as NIC, multiport switch, firewall, test/measurement environment, and more.

    +

    Features list:

    +
      +
    • Field Programmable Gate (FPGA) Logic
        +
      • Xilinx Virtex-7 690T
        • +
      • 693,120 logic cells
        • +
      • 52,920 Kbit block RAM
        • +
      • up to 10,888 Kbit distributed RA
        • +
      • 30 GTH (up to 13.1Gbps) Transceivers
        • +
      • Fully programmable by the user
        • +
      • +
    • 10-Gigabit Ethernet Connection
        +
      • Connector block on left of PCB interfaces to 4 external SFP+ ports
        • +
      • Directly connected to the FPGA.
        • +
      • Wire-speed processing on all ports at all time using FPGA logic.
        • +
      • +
    • Quad Data Rate Static Random Access Memory (QDRII+ SRAM)
        +
      • Suitable for storing and forwarding table data
        • +
      • 500MHz Quad data rate (2 Giga transactions every second), synchronous with the logic
        • +
      • Three parallel banks of 72 MBit QDRII+ memories
        • +
      • Total capacity: 27 MBytes
        • +
      • Cypress: CY7C25652KV18-500BZC
        • +
      • +
    • Double-Date Rate Random Access Memory (DDR3 DRAM)
        +
      • Suitable for packet buffering
        • +
      • Two replaceable DDR3-SoDIMM modules
        • +
      • 933MHz clock (1866MT/s)
        • +
      • 238.8 Gbps peak memory throughput
        • +
      • Total capacity: 8 GBytes (Supports up to 32 GBytes)
        • +
      • Micron: MT8KTF51264HZ-1G9E5
        • +
      • +
    • PCI Express Gen. 3
        +
      • Third generation PCI Express interface, 8Gbps/lane
        • +
      • 8 lanes (x8)
        • +
      • Hard IP
        • +
      • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
        • +
      • +
    • Expansion Interfaces
        +
      • Fully compliant VITA-57 FMC HPC connector, including 10 high-speed serial links
        • +
      • SAMTEC QTH-DP connector, connected to 8 high-speed serial links
        • +
      • Allowing to connect additional 18 GTH transceivers
        • +
      • Digilent PMOD expansion connector
        • +
      • +
    • Storage
        +
      • 2 SATA connectors
        • +
      • Micro-SD slot
        • +
      • 2 FLASH devices, each 512Mbit (1Gbit total)
        • +
      • +
    • Additional Features
        +
      • Clock recovery circuit
        • +
      • Voltage sensors
        • +
      • Current sensors
        • +
      • User LEDs & Push Buttons
        • +
      • +
    • Standard PCIe Form Factor
        +
      • Standard PCIe card
        • +
      • Full length, full height
        • +
      • +
    • Flexible, Open-source code
      • +
    +
    +

    A full description of the board and its potential use cases is provided in the following paper:

    +

    Noa Zilberman, Yury Audzevich, G. Adam Covington, Andrew W. Moore, 'NetFPGA SUME: Toward 100 Gbps as Research Commodity,' IEEE Micro, vol.34, no.5, pp.32,41, September-October 2014 (official version) (pdf)

    +

    Please use this citation as the canonical reference for NetFPGA-SUME.

    +
    +
    +
    +
    +
    + +
    +

    To see the NetFPGA-SUME repository and Wiki you will need to register.

    +

    Reference Projects

    + + + + + + + + + + + + + + + + + + + + + + + + + + +
    TitleOrganisationDocumentation
    Reference SwitchUniversity of CambridgeWiki
    Reference Switch LiteUniversity of CambridgeWiki
    Reference NICUniversity of CambridgeWiki
    Reference RouterUniversity of CambridgeWiki
    +
    +
    + +
    +
    +
    + +
    +
    +

    Where can I buy a NetFPGA SUME Platform?

    + +

    It seems that my board is broken, what should I do?

    + +

    What if I have Hardware problems with my board?

    + +

    What if I have Software problems with my board?

    + +

    You can change your ideas and questions with the NetFPGA SUME community, please register here.

    +

    How can I get involved with the NetFPGA project?

    + +

    How can I obtain the gateware and software package?

    + +

    Digilent Hardware documentation wiki about NetFPGA SUME board here.

    +
    +

    Once you have used the NetFPGA, we hope that you will contribute to the project.

    +

    You can find our Wiki here.

    +
    +
    +
    +
    + +
    +
    + +
    + + + + + + + + + + + diff --git a/Publications.html b/Publications.html new file mode 100644 index 0000000..2ee3b57 --- /dev/null +++ b/Publications.html @@ -0,0 +1,734 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    Publications featuring NetFPGA

    +

    A partial list of publications using the NetFPGA platform.

    +

    The links for the addresses are, where possible, doi.org links.

    +
    +
    + + +
    + +
    + + +
    +
    + + +
    +
    +
    + +
    + +
    +
    + +
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    + +
    + +
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    + +
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    + +
    + +
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    + +
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    + +
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    + +
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    + +
    + +
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    + +
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    + +
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    + +
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    +
    + +
    +
  • Antichi, G., Callegari, C., Giordano, S. (2012, December). An open hardware implementation of CUSUM based Network Anomaly Detection. Globecom. IEEE.
    • +
  • Rojas, E., Naous, J., Ibáñez, G., Recio, C. (2012, October). Dynamic Load Routing-Path Diversity in a Network of ARP-Path NetFPGA Switches. Conference on Local Computer Networks (LCN). IEEE.
    • +
  • Huang, T. Y., Handigol, N., Heller, B., McKeown, N., & Johari, R. (2012, November). Confused, timid, and unstable: picking a video streaming rate is hard. In Proceedings of the 2012 ACM conference on Internet measurement conference (pp. 225-238). ACM.
    • +
  • Matias, J., Jacob, E., Higuero, M., & Toledo, N. (2012, June). Extending Neutrality to Experimental Facilities. In ACCESS 2012, The Third International Conference on Access Networks (pp. 14-20).
    • +
  • Liu, X., Wada, A., Xing, T., Juluri, P., Sato, Y., Ata, S., ... & Medhi, D. (2012, April). SeRViTR: A framework for trust and policy management for a secure Internet and its proof-of-concept implementation. In Network Operations and Management Symposium (NOMS), 2012 IEEE (pp. 1159-1166). IEEE.
    • +
  • Matias, J., Tornero, B., Mendiola, A., Jacob, E., & Toledo, N. (2012, October). Implementing Layer 2 Network Virtualization using OpenFlow: Challenges and Solutions. In Software Defined Networking (EWSDN), 2012 European Workshop on (pp. 30-35). IEEE.
    • +
  • Handigol, N., Heller, B., Jeyakumar, V., Lantz, B., & McKeown, N. (2012, December). Reproducible network experiments using container-based emulation. In Proceedings of the 8th international conference on Emerging networking experiments and technologies (pp. 253-264). ACM.
    • +
  • Xie, D., Ding, N., Hu, Y. C., & Kompella, R. (2012). The only constant is change: incorporating time-varying network reservations in data centers. ACM SIGCOMM Computer Communication Review, 42(4), 199-210.
    • +
  • Hu, J. W., Huang, W. Y., Tseng, H. M., Lee, H. L., Ku, L. C., Lin, S. C., ... & Yang, C. S. (2012, July). Future Internet in Taiwan: Design and Research Activities over TWAREN Network. In Innovative Mobile and Internet Services in Ubiquitous Computing (IMIS), 2012 Sixth International Conference on (pp. 329-333). IEEE.
    • +
  • Seddiki, M. S., & Frikha, M. (2012, July). Resource Allocation for Virtual Routers through Non-Cooperative Games. In Computer Communications and Networks (ICCCN), 2012 21st International Conference on (pp. 1-6). IEEE.
    • +
  • Sonkoly, B., Gulyas, A., Nemeth, F., Czentye, J., Kurucz, K., Novak, B., & Vaszkun, G. (2012, October). On QoS Support to Ofelia and OpenFlow. In Software Defined Networking (EWSDN), 2012 European Workshop on (pp. 109-113). IEEE.
    • +
  • Gibb, G., Zeng, H., & McKeown, N. (2012, August). Outsourcing network functionality. In Proceedings of the first workshop on Hot topics in software defined networks (pp. 73-78). ACM.
    • +
  • Mendonca, M., Seetharaman, S., & Obraczka, K. (2012, June). A flexible in-network IP anonymization service. In Communications (ICC), 2012 IEEE International Conference on (pp. 6651-6656). IEEE.
    • +
  • Mirkovic, J., Shi, H., & Hussain, A. (2012, November). Reducing allocation errors in network testbeds. In Proceedings of the 2012 ACM conference on Internet measurement conference (pp. 495-508). ACM.
    • +
  • Corin, R. D., Gerola, M., Riggio, R., De Pellegrini, F., & Salvadori, E. (2012, October). VeRTIGO: Network Virtualization and Beyond. In Software Defined Networking (EWSDN), 2012 European Workshop on (pp. 24-29). IEEE.
    • +
  • Fotiou, N., Nikander, P., Trossen, D., & Polyzos, G. C. (2012). Developing information networking further: From PSIRP to PURSUIT. In Broadband Communications, Networks, and Systems (pp. 1-13). Springer Berlin Heidelberg.
    • +
  • Groleat, T., Arzel, M., & Vaton, S. (2012, August). Hardware acceleration of SVM-based traffic classification on FPGA. In Wireless Communications and Mobile Computing Conference (IWCMC), 2012 8th International (pp. 443-449). IEEE.
    • +
  • Konorski, J., Pacyna, P., Kolaczek, G., Kotulski, Z., Cabaj, K., & Szalachowski, P. (2012). A Virtualization-Level Future Internet Defense-in-Depth Architecture. In Recent Trends in Computer Networks and Distributed Systems Security (pp. 283-292). Springer Berlin Heidelberg.
    • +
  • Jiang, W., Ren, F., Shu, R., & Lin, C. (2012, March). Sliding Mode Congestion Control for data center Ethernet networks. In INFOCOM, 2012 Proceedings IEEE (pp. 1404-1412). IEEE.
    • +
  • Revsbech, K., Madsen, T. K., & Schioler, H. (2012, November). High precision testbed to evaluate ethernet performance for in-car networks. In ITS Telecommunications (ITST), 2012 12th International Conference on (pp. 548-552). IEEE.
    • +
  • Tarasiuk, H., Hanczewski, S., Kaliszan, A., Szuman, R., Ogrodowczyk, L., Olszewski, I., ... & Wisniewski, P. (2012, October). A proposal of the IPv6 QoS system implementation in virtual infrastructure. In Telecommunications Network Strategy and Planning Symposium (NETWORKS), 2012 XVth International (pp. 1-6). IEEE.
    • +
  • Tran, N. T., Tomiyama, S., Kittitornkun, S., & Vu, T. H. (2012, May). TCP reassembly for signature-based Network Intrusion Detection systems. In Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2012 9th International Conference on (pp. 1-4). IEEE.
    • +
  • Anand, M., Fischmeister, S., Lee, I., & Phan, L. T. (2012). State-based scheduling with tree schedules: analysis and evaluation. Real-Time Systems, 48(4), 430-462.
    • +
  • Jiang, W., Ren, F., Lin, C., & Stojmenovic, I. (2012, March). Analysis of backward congestion notification with delay for enhanced ethernet networks. In INFOCOM, 2012 Proceedings IEEE (pp. 2961-2965). IEEE.
    • +
  • Lockwood, J. W., Gupte, A., Mehta, N., Blott, M., English, T., & Vissers, K. (2012, August). A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). In High-Performance Interconnects (HOTI), 2012 IEEE 20th Annual Symposium on (pp. 9-16). IEEE.
    • +
  • Mehmood, M. A., Wundsam, A., Uhlig, S., Levin, D., Sarrar, N., & Feldmann, A. (2012). QoE-lab: Towards evaluating quality of experience for future internet conditions. In Testbeds and Research Infrastructure. Development of Networks and Communities (pp. 286-301). Springer Berlin Heidelberg.
    • +
  • Tarasiuk, H., & Rogowski, J. (2012, July). On the signaling system in the IPv6 QoS Parallel Internet. In Communication Systems, Networks & Digital Signal Processing (CSNDSP), 2012 8th International Symposium on (pp. 1-6). IEEE.
    • +
  • Liu, X., Fouli, K., Kang, R., & Maier, M. (2012). Network-Coding-Based Energy Management for Next-Generation Passive Optical Networks. Journal of Lightwave Technology, 30(6), 864-875.
    • +
  • Yin, D., & Li, G. (2012). Scalable MapReduce Framework on FPGA Accelerated Commodity Hardware. In Internet of Things, Smart Spaces, and Next Generation Networking (pp. 280-294). Springer Berlin Heidelberg.
    • +
  • Pries, R., Jarschel, M., & Goll, S. (2012, June). On the usability of OpenFlow in data center environments. In Communications (ICC), 2012 IEEE International Conference on (pp. 5533-5537). IEEE.
    • +
  • Ghobadi, M., Salmon, G., Ganjali, Y., Labrecque, M., & Steffan, J. G. (2012, August). Caliper: Precise and responsive traffic generator. In High-Performance Interconnects (HOTI), 2012 IEEE 20th Annual Symposium on (pp. 25-32). IEEE.
    • +
  • Meng, W., Wang, Y., Hu, C., He, K., Li, J., & Liu, B. (2012, March). Greening the Internet Using Multi-frequency Scaling Scheme. In Advanced Information Networking and Applications (AINA), 2012 IEEE 26th International Conference on (pp. 928-935). IEEE.
    • +
  • Papadimitriou, K., Vatsolakis, C., & Pnevmatikatos, D. (2012, July). Invited paper: Acceleration of computationally-intensive kernels in the reconfigurable era. In Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on (pp. 1-5). IEEE.
    • +
  • Zhang, F., Xie, Y., Liu, J., Luo, L., Ning, Q., & Wu, X. (2012, August). ITester: A FPGA based high performance traffic replay tool. In Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on (pp. 699-702). IEEE.
    • +
  • Maravic, I., & Smiljanic, A. (2012, June). MPLS implementation for the Linux kernel. In High Performance Switching and Routing (HPSR), 2012 IEEE 13th International Conference on (pp. 23-28). IEEE.
    • +
  • Li, J., Li, Y., Li, H., Zhu, Z., Zhang, H., & Chen, F. (2012, July). A synchronous algorithm of network coding with hardware logic. In ICT and Energy Efficiency and Workshop on Information Theory and Security (CIICT 2012), Symposium on (pp. 82-87). IET.
    • +
  • Wang, K., Yang, B., Chen, Z., & Sun, T. (2012). Design and Implementation of FPGA Network Simulation and Verification Platform. In Advances in Computer Science and Information Engineering (pp. 659-664). Springer Berlin Heidelberg.
    • +
  • Reforgiato, D., Lombardo, A., Davoli, F., Fialho, L., Collier, M., Donadio, P., ... & Bruschi, R. (2012, June). Exporting data-plane energy-aware capabilities from network devices toward the control plane: The Green Abstraction Layer. In Networks and Optical Communications (NOC), 2012 17th European Conference on (pp. 1-6). IEEE.
    • +
  • Dixit, A. A., Prakash, P., Kompella, R. R., & Hu, C. (2012, June). On the efficacy of fine-grained traffic splitting protocols in data center networks. In Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems (pp. 411-412). ACM.
    • +
  • Antichi, G., Giordano, S., Miller, D. J., & Moore, A. W. (2012, April). Enabling open-source high speed network monitoring on NetFPGA. In Network Operations and Management Symposium (NOMS), 2012 IEEE (pp. 1029-1035). IEEE.
    • +
  • Unnikrishnan, D., Vadlamani, R., Liao, Y., Crenne, J., Gao, L., & Tessier, R. (2012). Reconfigurable Data Planes for Scalable Network Virtualization.
    • +
  • Chasaki, D., & Wolf, T. (2012). Attacks and Defenses in the Data Plane of Networks.
    • +
  • Carvajal, G., Wu, C., & Fischmeister, S. (2012). Evaluation of Communication Architectures for Switched Real-time Ethernet.
    • +
  • Thinh, T. N., Hieu, T. T., & Kittitornkun, S. (2012, May). A FPGA-based deep packet inspection engine for Network Intrusion Detection System. In Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2012 9th International Conference on (pp. 1-4). IEEE.
    • +
  • Chydzinski, A., Rawski, M., Wisniewski, P., Adamczyk, B., Olszewski, I., Szotkowski, P., ... & Parniewicz, D. (2012, August). Virtualization Devices for Prototyping of Future Internet. In Software Engineering, Artificial Intelligence, Networking and Parallel & Distributed Computing (SNPD), 2012 13th ACIS International Conference on (pp. 672-678). IEEE.
    • +
  • Michalski, M. (2012, July). The configurations for experimental study of the network performance. In Communication Systems, Networks & Digital Signal Processing (CSNDSP), 2012 8th International Symposium on (pp. 1-6). IEEE.
    • +
  • Guo, F., Ormond, O., Fialho, L., Collier, M., & Wang, X. (2012). Power consumption analysis of a NetFPGA based router. The Journal of China Universities of Posts and Telecommunications, 19, 94-99.
    • +
  • Gringoli, F., Nava, L., Este, A., & Salgarelli, L. (2012, August). MTCLASS: Enabling statistical traffic classification of multi-gigabit aggregates on inexpensive hardware. In Wireless Communications and Mobile Computing Conference (IWCMC), 2012 8th International (pp. 450-455). IEEE.
    • +
  • Thanh, N. H., Nam, P. N., Truong, T. H., Hung, N. T., Doanh, L. K., & Pries, R. (2012, August). Enabling experiments for energy-efficient data center networks on OpenFlow-based platform. In Communications and Electronics (ICCE), 2012 Fourth International Conference on (pp. 239-244). IEEE.
    • +
  • Muehlbach, S., & Koch, A. (2012, October). Malacoda: towards high-level compilation of network security applications on reconfigurable hardware. In Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems (pp. 247-258). ACM.
    • +
  • Belias, A., Koutsoumpos, V., Manolopoulos, K., & Kachris, C. (2012). Reconfigurable hardware applications on NetFPGA for network monitoring in large area sensor networks. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment.
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  • Lombardo, A., Reforgiato, D., Riccobene, V., & Schembra, G. (2012, October). A Markov model to control heat dissipation in open multi-frequency green routers. In Sustainable Internet and ICT for Sustainability (SustainIT), 2012 (pp. 1-9). IEEE.
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  • Vu, T. H., Nam, P. N., Thanh, T., Linh, N. D., Thien, T. D., & Thanh, N. H. (2012, October). Power aware OpenFlow switch extension for energy saving in data centers. In Advanced Technologies for Communications (ATC), 2012 International Conference on (pp. 309-313). IEEE.
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  • Xu, Y., Gu, R., & Ji, Y. (2012, September). Network traffic on-line classification using decision tree fast parallel processing strategy. In Network Infrastructure and Digital Content (IC-NIDC), 2012 3rd IEEE International Conference on (pp. 339-343). IEEE.
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  • Orosz, P., Skopko, T., & Imrek, J. (2012, October). A NetFPGA-based network monitoring system with multi-layer timestamping: Rnetprobe. In Telecommunications Network Strategy and Planning Symposium (NETWORKS), 2012 XVth International (pp. 1-6). IEEE.
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  • Liu, G., & Neufeld, N. (2012, June). LHCb: The LHCb off-Site HLT Farm Demonstration. In Conference: 18th IEEE Real-Time Conference 2012 (No. Poster-2012-238).
    • +
  • Hieu, T. T., Thinh, T. N., & Tomiyama, S. (2013). ENREM: An Efficient NFA-based Regular Expression Matching Engine on Reconfigurable Hardware for NIDS. Journal of Systems Architecture.
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  • Xin Liu; Fouli, K.; Rui Kang; Maier, M.; , 'Network-Coding-Based Energy Management for Next-Generation Passive Optical Networks,' Lightwave Technology, Journal of , vol.30, no.6, pp.864-875, March 15, 2012
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Editing either one of these will affect the layout of the page. + +To edit the layout with precision edit default.html because page.html uses default.html as its layout + +Editing either of these will edit the layout of every page, however changing page.html won't change the layout on the ecosystem page. To change that edit the ecosystem-layout.html. + +### Editing the layout of a specific page + +To edit the specific of a particular page create a new html file in the _layouts folder and on the page you are editing change the layout to be the new layout you have just made. + +## How to edit a particular page + +### How to edit the Home Page + +To edit the Home page edit the index.html file. + +The recent news section can be edited by editing the most-recent-news-posts.html found in the _includes folder + +### How to edit the pages for each system + +#### How to edit the NetFPGA PLUS page + +Edit the NetFGPA-PlUS.html file. + +#### How to edit the NetFPGA SUME page + +Edit the NetFPGA-SUME.html file. + +#### How to edit the NetFPGA CML page + +Edit the NetFPGA-CML.html file. + +#### How to edit the NetFPGA 10G page + +Edit the NetFPGA-10G.html file. + +#### How to edit the NetFPGA 1G page + +Edit the NetFPGA-1G.html file. + +### How to edit the about page + +Edit the About.html file. + +All logos can be found sorted into hosts and supporters in the Logos folders in the images folder in the assets folder. + +### How to edit the ecosystem page + +To edit the text at the top of the ecosystem edit the ecosystem.html page. + +To edit information on one of the cards check the ecosystem subfolder of the _posts folder. Look for the file with the name of the ecosystem part after the date. + +To add a new card check [example-ecosystem.md](/_posts/ecosystem/example-ecosystem.md) for the metadata tags that are needed as well as the purpose of each one. The ecosystem file should be named with the date it was added to the site in the format \-\-\-\. The date used in the name of the file should be the date the file was added to the website. + +To add a new button to the ecosystem page copy and paste one of the buttons that is already in [ecosystem-buttons](/_includes/ecosystem-buttons.html) and then replace the specifics with the relevant information. And make sure that the button is in the correct section on the page. + +***If adding new organisations, organisation types, product types, target platforms please make sure to check [adding-to-javascript.md](/_posts/ecosystem/adding-to-javascript.md)*** + +### How to edit the Publications to page + +Each years publications are in the _includes folder with the naming system of \-Publications.html +To add publications to a particular year edit the corresponding file for the year. + +To add a new years publications follow the same format as the most recent years one. But where it uses a year use the current year. Then add the class "collapsed" to the div with the button in and remove the "show" class from the div with the list of publications in. + +Then add: + +*{% include \-Publications.html %}* + +*\* + +*\* + +to Publications.html + +### How to edit the news and events page + +To edit the functionality of the checkboxes edit the [news-and-events.html](/news-and-events.html) file. + +To change the information about a specific event/piece of news look for the file you're looking for in the news-and-events subfolder of the _posts folder and all files that show up on the website have file names looking like \-\-\-.md + +To add a new piece of news check [example-news-post.md](/_posts/news-and-events/example-news-post.md) for all that's required. + +to add a new event check [example-events-post.md](/_posts/news-and-events/example-events-post.md) for all that's required. + +For events that have their information hosted on the NetFPGA website to edit those files these pages can be found in the _pages folder with the same naming format as the the events. + +If you want to add a new metadata field to the posts first add it to the example posts for the relevant categories and it what it is used for. Then add it to the rest of the affected posts. Then in the news and events file add + +*{% if post.\<metadata tag\> %}* + +*\<appropriate tag\>{{ post.\<metadata tag\> }}\<\/appropriate tag\>* + +*{% endif %}* + +### How to edit the why NetFPGA page + +Edit the why-NetFPGA.html + +<hr> +<br> + +Most of the css used in the website is Bootstrap but the non-bootstrap css can be found [here](/assets/css/_sass/custom.scss). diff --git a/SUME-reg-form.html b/SUME-reg-form.html new file mode 100644 index 0000000..bc8f202 --- /dev/null +++ b/SUME-reg-form.html @@ -0,0 +1,121 @@ +<!DOCTYPE html> +<html lang="en"> +<head> + <meta charset="utf-8" /> + <meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no"/> + <meta name="description" content="A business home page starter template for Bootstrap 4 featuring marketing boxes and a full width image header." /> + <meta name="author" content="" /> + + <title>NetFPGA + + + + + + + + + + + + + +
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    NetFPGA

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    NetFPGA SUME Beta Registration

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    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
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    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
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    Copyright © NetFPGA 2021

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    + + + + + + + + diff --git a/_pages/10G-License.html b/_pages/10G-License.html new file mode 100644 index 0000000..c76317f --- /dev/null +++ b/_pages/10G-License.html @@ -0,0 +1,154 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
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    NetFPGA

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    License

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    The NetFPGA-10G code base is covered under version 2.1 of the GNU LGPL. Xilinx IP, however, is an exception to this and covered under Xilinx licenses. The following is information on how to obtain a license for various Xilinx IP:

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    Xilinx 10 Gigabit Ethernet Media Access Controller.

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    Anybody can get an evaluation license for free which allows the end-user to simulate the system, however bitstream generation is limited. For a full hardware license, academic end-users can request a donation through the Xilinx University Program. Other end-users have to purchase a "SignOnce" license. Evaluation license or the full license can get obtained through the links on the 10G MAC page. To obtain a free full hardware license for academic end-users, please visit the Xilinx University Program and submit a donation request for the following part number: EF-DI-10GEMAC-SITE.
    +This webpage explains how to install the license.

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    Xilinx XAUI

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    Xilinx XAUI core is included in Xilinx ISE installation at no additional charge. The "make cores" script handles the core generation automatically. Please refer to "Installation" section of Getting Started Guide

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    Other Xilinx EDK cores

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    Xilinx EDK cores are included in Xilinx ISE installation at no additional charge. The "make cores" script copies those cores to NetFPGA-10G library automatically. Please refer to "Installation" section of Getting Started Guide.

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    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
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    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
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    Copyright © NetFPGA 2021

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    + + + + + + + + diff --git a/_pages/1G-License.html b/_pages/1G-License.html new file mode 100644 index 0000000..bb85c74 --- /dev/null +++ b/_pages/1G-License.html @@ -0,0 +1,128 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
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    NetFPGA

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    License

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    The NetFPGA code is distributed under a BSD-style license shown below. Please make sure you read and understand it. The design of the board itself is also available freely.

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    Copyright © 2006-2012 The Board of Trustees of The Leland Stanford Junior University

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    We are making the NetFPGA tools and associated documentation (Software) available for public use and benefit with the expectation that others will use, modify and enhance the Software and contribute those enhancements back to the community. However, since we would like to make the Software available for broadest use, with as few restrictions as possible permission is hereby granted, free of charge, to any person obtaining a copy of this Software) to deal in the Software under the copyrights without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

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    The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

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    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

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    The name and trademarks of copyright holder(s) may NOT be used in advertising or publicity pertaining to the Software or any derivatives without specific, written prior permission.

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    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
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    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
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    Copyright © NetFPGA 2021

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    + + + + + + + + diff --git a/_pages/2007-08-24-Hot-Interconnects-Tutorial.html b/_pages/2007-08-24-Hot-Interconnects-Tutorial.html new file mode 100644 index 0000000..e70d4b7 --- /dev/null +++ b/_pages/2007-08-24-Hot-Interconnects-Tutorial.html @@ -0,0 +1,295 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
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    NetFPGA

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    Hot Interconnects Tutorial

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    Hands-on with the NetFPGA to build a Gigabit-rate Router

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    Presented by: Nick McKeown, John W. Lockwood, Jad Naous, Glen Gibb, Adam Covington

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    Date: Friday, August 27, 2007

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    Time: 9am - 5pm

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    Location: Stanford University, Gates Building, Room 104.

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    Abstract

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    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

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    Background

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    Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at the half-day SIGMETRICS tutorial on June 12, 2007.

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    + +A Photo from the tutorial + +
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    Outline

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    • Introduction to the operation of an Internet Router
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      • Control Plane
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        • Routing protocols
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        • Routing table
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        • Management interfaces
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      • Datapath
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        • Longest Prefix Match (LPM)
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        • Classless Interdomain Routing (CIDR)
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        • Header processing
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        • Packet buffering
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    • The NetFPGA Router
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      • Hardware
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        • Gigabit Ethernet interfaces
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        • Field Programmable Gate Array (FPGA) Logic
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        • Random Access Memory (RAM)
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      • Software
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        • Kernel-space driver
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        • User-space applications
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        • PCI interface
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    • Demonstration Topology
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        • Hardware
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          • Network of ten routers
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          • Ethernet switch
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          • Video server
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          • High Definition (HD) video client
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        • Software
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          • PW-OSPF
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          • Routing tables
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          • Dynamic re-routing
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    • Integrated Circuit Design
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      • Technologies
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        • Look-Up Tables (LUTs)
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        • Configurable Logic Blocks (CLBs)
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        • Field Programmable Gate Arrays (FPGAs)
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      • Verilog Hardware Description Language (HDL)
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        • Registers, integers, arrays
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        • Multiplexers
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        • Synchronous storage elements
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        • Finite State Machines (FSMs)
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      • Hardware Debug
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        • Waveform monitor
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        • In-circuit logic emulation
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    • NetFPGA System Components
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      • Synthesis of tutorial router
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      • Java-based Graphical User Interface (GUI)
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        • Configuration
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        • Statistics
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      • Router Architecture
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        • Pipeline
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        • Queues
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    • Buffer Size Experiment
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      • Experiment with TCP/IP flows
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        • Rule-of-thumb for the buffer size
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        • Round-trip propation delay
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        • Capacity of bottlneck link
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        • Number of active flows
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      • Lower delay with smaller queues
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    • Enhanced Router
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      • Additional hardware
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        • Event capture module
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        • Rate limiter
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        • Delay module
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      • Experiments
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        • Netperf
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        • HD video transport
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      • Life of packet through the system
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        • Description of blocks
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        • Waveforms
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    About the presentors

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    • Nick McKeown
      Nick McKeown is a Professor of Electrical Engineering and Computer Science and Faculty Director of the Clean Slate Program at Stanford University. He received his Phd from the University of California at Berkeley in 1995. From 1986-1989, he worked for Hewlett-Packard Labs in their network and communications research group in Bristol, England. During the Spring of 1995, he worked briefly for Cisco Systems where he helped architect their GSR 12000 router. In 1997 Nick co-founded Abrizio Inc., where he was CTO. Abrizio is now part of PMC-Sierra. He was co-founder and CEO of Nemo Systems, which is now part of Cisco Systems.

      Nick McKeown is the STMicroelectronics Faculty Scholar, the Robert Noyce Faculty Fellow, a Fellow of the Powell Foundation and the Alfred P. Sloan Foundation, and recipient of a CAREER award from the National Science Foundation. In 2000, he received the IEEE Rice Award for the best paper in communications theory. Nick is a Fellow of the Royal Academy of Engineering (UK), and a Fellow of the IEEE and the ACM, and British Computer Society Lovelace Medal Winner, 2005. He served as an Editor for the IEEE Transactions on Communications and ACM/IEEE Transactions on Networking, and as a Guest Editor for IEEE Journal on Selected Areas on Communications, IEEE Networks Magazine and IEEE Communications Magazine, and chaired the Technical Advisory Committee for ACM Sigcomm. Nick's research interests include the architecture of the future Internet, the architecture, analysis and design of high performance switches and Internet routers, IP lookup and classification algorithms, scheduling algorithms, congestion control, routing protocols and network processors.
      • +
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    • John W. Lockwood
      John W. Lockwood is a Consulting Associate Professor at Stanford University. At Stanford, he leads the NetFPGA Alpha and Beta release programs and organizes the worldwide tutorial program. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology. Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies. Dr. Lockwood earned his Ph.D from the Department of Electrical and Computer Engineering at the University of Illinois.

      John Lockwood has served as the principal investigator on grants from the National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.
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    • Jad Naous
      Jad Naous received his B.Eng. degree in Computer Engineering from McGill University in 2005, and his M.S.E.E. degree from Stanford University in 2007. He is currently pursuing a doctorate in Electrical Engineering at Stanford University. He has previously worked as a Graduate Intern for Sun Microsystems Labs in 2006, where he worked on the next generation switch project. In 2007, he joined Agilent Technologies Labs as a Graduate Intern where he helped implement special devices for the IEEE1588 Precision Time Protocol using NetFPGA.
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    • Glen Gibb
      Glen is a PhD candidate in Electrical Engineering at Stanford University. He received his Master of Science in Electrical Engineering from Stanford University and a Bachelor of Science and a Bachelor of Engineering from The University of Melbourne in Australia. He has been working on the NetFPGA platform since 2004 and was the lead designer for the current hardware version.
      • +
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    • Adam Covington
      Adam is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. He is currently working on the NetFPGA project, which enables researchers and instructors to build hardware-accelerated networking systems. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. While at Washington University he designed, and implemented clustering algorithms on FPGAs and supported a hardware accelerated classification system on the FPX platform. Adam’s current research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Adam completed a Bachelor of Science degree in Computer Engineering from Western Michigan University in April 2003 and accepted a Distinguished Masters of Science Fellowship from Washington University. He completed his Masters of Science degree in Computer Science and Engineering from Washington University in December 2006. Adam continues to provide support for the NetFPGA project which includes helping users worldwide as well as arranging and presenting tutorials.
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    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
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    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
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    + +

    Copyright © NetFPGA 2021

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    + +
    + + + + + + + + diff --git a/_pages/2008-02-06-NetFPGA-Sydney-Tutorial.html b/_pages/2008-02-06-NetFPGA-Sydney-Tutorial.html new file mode 100644 index 0000000..bb63df6 --- /dev/null +++ b/_pages/2008-02-06-NetFPGA-Sydney-Tutorial.html @@ -0,0 +1,329 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
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    NetFPGA

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    NetFPGA Sydney Tutorial

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    Hands-on with the NetFPGA to build a Gigabit-rate Router at NICTA

    + +
    + +

    Presented by: John W. Lockwood, Glen Gibb, and Jad Naous of the: High Performance Network Group at Stanford University

    + +

    Hosted by: Lavy Libman and Philip Allen NICTA (National ICT Australia) and School of Electrical Engineering and Telecommunications The University of New South Wales (UNSW)

    + +

    Date: Wednesday, February 6, 2008

    + +

    Time: 9am - 5pm

    + +

    Location: Lab343A at the University of New South Wales School of Electrical Engineering and Telecommunications building (G17) Kensington campus, Sydney, Australia

    + +
    + +

    To Register to attend, send email here with a subject line of "I plan to attend the NetFPGA tutorial" and a message that includes your name, title, organisation, and contact information.

    + +
    +
    + +

    Abstract

    + +
    + +

    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

    +
    +

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

    +
    +

    This full-day hands-on tutorial will be held in Sydney on Wednesday, February 6.

    + +
    +
    + +

    Background

    + +
    + +

    Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at the Hot Interconnects tutorial and the SIGMETRICS tutorials in 2007.

    + +
    +
    + +A photo of a NetFPGA tutorial + +
    +
    + +

    Outline

    + +
    + +
      +
    • Introduction to the operation of an Internet Router
      • +
        +
      • Control Plane
        • +
          +
        • Routing protocols
          • +
        • Routing table
          • +
        • Management interfaces
          • +
        +
      • Datapath
        • +
          +
        • Longest Prefix Match (LPM)
          • +
        • Classless Interdomain Routing (CIDR)
          • +
        • Header processing
          • +
        • Packet buffering
          • +
        +
      +
    • The NetFPGA Router
      • +
        +
      • Hardware
        • +
          +
        • Gigabit Ethernet interfaces
          • +
        • Field Programmable Gate Array (FPGA) Logic
          • +
        • Random Access Memory (RAM)
          • +
        +
      • Software
        • +
          +
        • Kernel-space driver
          • +
        • User-space applications
          • +
        • PCI interface
          • +
        +
      +
    • Demonstration Topology
      • +
        +
          +
        • Hardware
          • +
            +
          • Network of ten routers
            • +
          • Ethernet switch
            • +
          • Video server
            • +
          • High Definition (HD) video client
            • +
          +
        • Software
          • +
            +
          • PW-OSPF
            • +
          • Routing tables
            • +
          • Dynamic re-routing
            • +
          +
        +
      +
    • Integrated Circuit Design
      • +
        +
      • Technologies
        • +
          +
        • Look-Up Tables (LUTs)
          • +
        • Configurable Logic Blocks (CLBs)
          • +
        • Field Programmable Gate Arrays (FPGAs)
          • +
        +
      • Verilog Hardware Description Language (HDL)
        • +
          +
        • Registers, integers, arrays
          • +
        • Multiplexers
          • +
        • Synchronous storage elements
          • +
        • Finite State Machines (FSMs)
          • +
        +
      • Hardware Debug
        • +
          +
        • Waveform monitor
          • +
        • In-circuit logic emulation
          • +
        +
      +
    • NetFPGA System Components
      • +
        +
      • Synthesis of tutorial router
        • +
      • Java-based Graphical User Interface (GUI)
        • +
          +
        • Configuration
          • +
        • Statistics
          • +
        +
      • Router Architecture
        • +
          +
        • Pipeline
          • +
        • Queues
          • +
        +
      +
    • Buffer Size Experiment
      • +
        +
      • Experiment with TCP/IP flows
        • +
          +
        • Rule-of-thumb for the buffer size
          • +
        • Round-trip propation delay
          • +
        • Capacity of bottlneck link
          • +
        • Number of active flows
          • +
        +
      • Lower delay with smaller queues
        • +
      +
    • Enhanced Router
      • +
        +
      • Additional hardware
        • +
          +
        • Event capture module
          • +
        • Rate limiter
          • +
        • Delay module
          • +
        +
      • Experiments
        • +
          +
        • Netperf
          • +
        • HD video transport
          • +
        +
      • Life of packet through the system
        • +
          +
        • Description of blocks
          • +
        • Waveforms
          • +
        +
      +
    + +
    +
    + +

    About the presentors

    + +
    + +
      +
    • John W. Lockwood
      John W. Lockwood is a Consulting Associate Professor at Stanford University. At Stanford, he leads the NetFPGA Alpha and Beta release programs and organizes the worldwide tutorial program. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology. Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies. Dr. Lockwood earned his Ph.D from the Department of Electrical and Computer Engineering at the University of Illinois.

      John Lockwood has served as the principal investigator on grants from the National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.
      • +
      +
    • Glen Gibb
      Glen is a PhD candidate in Electrical Engineering at Stanford University. He received his Master of Science in Electrical Engineering from Stanford University and a Bachelor of Science and a Bachelor of Engineering from The University of Melbourne in Australia. He has been working on the NetFPGA platform since 2004 and was the lead designer for the current hardware version.
      • +
      +
    • Jad Naous
      Jad Naous received his B.Eng. degree in Computer Engineering from McGill University in 2005, and his M.S.E.E. degree from Stanford University in 2007. He is currently pursuing a doctorate in Electrical Engineering at Stanford University. He has previously worked as a Graduate Intern for Sun Microsystems Labs in 2006, where he worked on the next generation switch project. In 2007, he joined Agilent Technologies Labs as a Graduate Intern where he helped implement special devices for the IEEE1588 Precision Time Protocol using NetFPGA.
      • +
      +
    • Lavy Libman
      Lavy Libman received his B.Sc. degrees in Electrical Engineering and in Computer Engineering, and his M.Sc. and Ph.D. degrees in Electrical Engineering, from the Technion - Israel Institute of Technology, Haifa, Israel, in 1992, 1997, and 2003, respectively. He is currently a researcher at the Networked Systems research group at NICTA (formerly National ICT Australia), Sydney, which he joined in September 2003. He previously held several visiting and consulting positions, including with Bell Laboratories in summer 2002, where he participated in a research team on path restoration in optical networks, and with Millimetrix Broadband Networks in summer 2000, where he took part in the specification of the Unity. system. Between 1993 and 1999, he served as a computer engineer in the Israel Defence Forces.

      Dr. Libman is a member of the IEEE Communications Society. He currently co-chairs the Track on Protocols and Algorithms for Wireless Networks in ICCCN 2008. He was the chair of the Cross-Layer Design and Optimization track of ICCCN 2007 and a co-chair of the Workshop on Networking in Public Transport (WNEPT 2006). In addition, he serves as a technical program committee member for several international conferences, including IEEE Infocom, IEEE LCN, IEEE VTC, QShine, and WiOpt.

      Dr. Libman is a member and a local representative of the Australian Communications Research Network (ACoRN).
      • +
      +
    • Philip Allen
      Philip Allen works in the area of networking and photonics within the School of Electrical Engineering and Telecommunications at the University of New South Wales where he manages the networking laboratories. Philip earned his B.E. from UNSW and is working on a Masters of Business and Technology. Philip has worked has worked at Thorn-EMI Limited U.K. and Geoterrex (now Fugro Airborne Surveys).
      • +
    + +
    +
    + +

    Photos From the Event

    + +
    + + + +
    +
    + +

    To Attend this Event

    + +
    + +

    To Register to attend, send email here with a subject line of "I plan to attend the NetFPGA tutorial" and a message that includes your name, title, organisation, and contact information. For accomodations, rooms can be booked at hotels near UNSW

    + +
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    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2008-04-23-NetFPGA-Beijing-Tutorial.html b/_pages/2008-04-23-NetFPGA-Beijing-Tutorial.html new file mode 100644 index 0000000..4e07076 --- /dev/null +++ b/_pages/2008-04-23-NetFPGA-Beijing-Tutorial.html @@ -0,0 +1,170 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
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    +

    NetFPGA

    +
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    + + +
    +
    +
    +

    NetFPGA Beijing Tutorial

    + +
    +
    + +

    Hands-on with the to build a Gigabit-rate Router at Beijing Jiaotong University

    + +
    + +

    Presented by:John W. Lockwood and Jianying Luo of the: NetFPGA group at Stanford university, Kevin Xie and Walkie Que of the Xilinx University Program (XUP) in China, and Defeng Li of Huawei

    +

    Hosted by: Prof. Hongke Zhang

    +

    Sponsored by: Xilinx and Huawei

    +

    Date: April 23, 2008 and April 24, 2008

    +

    Time: 9am - 5pm (23rd) and 9am - Noon (24th/)

    +

    Location: Next Generation Internet Research Laboratory, Beijing Jiaotong University, No 3. of Shangyuan Residence Haidian District in Beijing, No. 411 South of the No. 9 Teaching Building, Beijing, China

    + +
    +
    + +

    Background

    + +
    + +

    This full-day tutorial extends the material presented at the Hot Interconnects tutorial and the SIGMETRICS tutorials in 2007.

    + +
    + +A photo from the tutorial + +
    + +Another photo from the tutorial + +
    +
    + +

    Photos from the Event

    + +
    + + + +
    +
    + +

    To Attend this Event

    + +
    + +

    To Register to attend, please submit a registration form and send an email here

    +

    [Registration for this event is now closed - Event at capacity]

    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2008-05-15-NetFPGA-Bangalore-Tutorial.html b/_pages/2008-05-15-NetFPGA-Bangalore-Tutorial.html new file mode 100644 index 0000000..9085d2f --- /dev/null +++ b/_pages/2008-05-15-NetFPGA-Bangalore-Tutorial.html @@ -0,0 +1,297 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA Bangalore Tutorial

    + +
    +
    + +

    Hands-on with the NetFPGA to build a Gigabit-rate Router at Indian Institute of Science (IISc)

    + +
    + +

    Presented by: John W. Lockwood and Jad Naous of the: High Performance Network Group at Stanford University and Kuruvilla Varghese of IISc.

    +

    Co-Hosted by: Veena Kumar, Xilinx University Program, India

    +

    Date: May 15-16, 2008

    +

    Time: 9am-5pm

    +

    Location: SDMP/Micro-electronics Lab, Room No: 207, Centre For Electronics Design and Technology, Indian Institute of Science, Bangalore, India

    + +
    +
    + +

    Abstract

    + +
    + +

    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

    +

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

    + +
    +
    + +

    Background

    + +
    + +

    Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at the Hot Interconnects tutorial and the SIGMETRICS tutorials in 2007.

    +
    +
    + +

    Outline

    + +
    + +
      +
    • Introduction to the operation of an Internet Router
      • +
        +
      • Control Plane
        • +
          +
        • Routing protocols
          • +
        • Routing table
          • +
        • Management interfaces
          • +
        +
      • Datapath
        • +
          +
        • Longest Prefix Match (LPM)
          • +
        • Classless Interdomain Routing (CIDR)
          • +
        • Header processing
          • +
        • Packet buffering
          • +
        +
      +
    • The NetFPGA Router
      • +
        +
      • Hardware
        • +
          +
        • Gigabit Ethernet interfaces
          • +
        • Field Programmable Gate Array (FPGA) Logic
          • +
        • Random Access Memory (RAM)
          • +
        +
      • Software
        • +
          +
        • Kernel-space driver
          • +
        • User-space applications
          • +
        • PCI interface
          • +
        +
      +
    • Demonstration Topology
      • +
        +
          +
        • Hardware
          • +
            +
          • Network of ten routers
            • +
          • Ethernet switch
            • +
          • Video server
            • +
          • High Definition (HD) video client
            • +
          +
        • Software
          • +
            +
          • PW-OSPF
            • +
          • Routing tables
            • +
          • Dynamic re-routing
            • +
          +
        +
      +
    • Integrated Circuit Design
      • +
        +
      • Technologies
        • +
          +
        • Look-Up Tables (LUTs)
          • +
        • Configurable Logic Blocks (CLBs)
          • +
        • Field Programmable Gate Arrays (FPGAs)
          • +
        +
      • Verilog Hardware Description Language (HDL)
        • +
          +
        • Registers, integers, arrays
          • +
        • Multiplexers
          • +
        • Synchronous storage elements
          • +
        • Finite State Machines (FSMs)
          • +
        +
      • Hardware Debug
        • +
          +
        • Waveform monitor
          • +
        • In-circuit logic emulation
          • +
        +
      +
    • NetFPGA System Components
      • +
        +
      • Synthesis of tutorial router
        • +
      • Java-based Graphical User Interface (GUI)
        • +
          +
        • Configuration
          • +
        • Statistics
          • +
        +
      • Router Architecture
        • +
          +
        • Pipeline
          • +
        • Queues
          • +
        +
      +
    • Buffer Size Experiment
      • +
        +
      • Experiment with TCP/IP flows
        • +
          +
        • Rule-of-thumb for the buffer size
          • +
        • Round-trip propation delay
          • +
        • Capacity of bottlneck link
          • +
        • Number of active flows
          • +
        +
      • Lower delay with smaller queues
        • +
      +
    • Enhanced Router
      • +
        +
      • Additional hardware
        • +
          +
        • Event capture module
          • +
        • Rate limiter
          • +
        • Delay module
          • +
        +
      • Experiments
        • +
          +
        • Netperf
          • +
        • HD video transport
          • +
        +
      • Life of packet through the system
        • +
          +
        • Description of blocks
          • +
        • Waveforms
          • +
        +
      +
    + +
    +
    + +

    About the presentors

    + +
    + +
      +
    • John W. Lockwood
      John W. Lockwood is a Consulting Associate Professor at Stanford University. At Stanford, he leads the NetFPGA Alpha and Beta release programs and organizes the worldwide tutorial program. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology. Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies. Dr. Lockwood earned his Ph.D from the Department of Electrical and Computer Engineering at the University of Illinois.

      John Lockwood has served as the principal investigator on grants from the National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.
      • +
      +
    • Kuruvilla Varghese
      Kuruvilla Varghese is a Principal Research Scientist at Centre for Electronics Design and Technology (CEDT), Indian Institute of Scinece, Bangalore. He is working in communications network group of CEDT. His main reserach interests are in Embedded systems, Communication networks and Digital VLSI systems. Presently he is working on High performance netwoking functions using Field Programmable Gate Arrays (FPGA).
      • +
      +
    • Jad Naous
      Jad Naous received his B.Eng. degree in Computer Engineering from McGill University in 2005, and his M.S.E.E. degree from Stanford University in 2007. He is currently pursuing a doctorate in Electrical Engineering at Stanford University. He has previously worked as a Graduate Intern for Sun Microsystems Labs in 2006, where he worked on the next generation switch project. In 2007, he joined Agilent Technologies Labs as a Graduate Intern where he helped implement special devices for the IEEE1588 Precision Time Protocol using NetFPGA.
      • +
    + +
    +
    + +

    To Attend this Event

    + +
    + +

    To Register to attend, Submit a registration form on-line
    Accomodations: Hoysala Guest House, IISc

    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2008-08-04-NetFPGA-Summer-Camp-2008.html b/_pages/2008-08-04-NetFPGA-Summer-Camp-2008.html new file mode 100644 index 0000000..0e767a6 --- /dev/null +++ b/_pages/2008-08-04-NetFPGA-Summer-Camp-2008.html @@ -0,0 +1,358 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA Summer Camp!

    + +
    +
    + +

    Earn a merit badge while building Internet routers and clean-slate switches. A 5-day summer camp will be held at Stanford University

    + +
    +

    Presented by: the NetFPGA Group

    +

    Open to: Professors teaching classes with NetFPGA and researchers interested in developing new hardware-accelerated network applications

    +

    Dates: Monday, August 4 - Friday, August 8, 2008

    +

    Time: 9am - 5pm. Bonfires and other evening events will be announced here.

    +

    Location: The Stanford University campus located between San Francisco and San Jose in the heart of the Silicon Valley.

    + +
    +
    + +

    Abstract

    + +
    + +

    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

    +

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

    + +
    +
    + +

    Background

    + +

    Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This week-long summercamp extends the material presented at the NetFPGA tutorials. Participants will be able to take home their NetFPGA systems at the end of the week-long camp.

    + +
    +
    + +Photo from the summer camp + +
    +
    + +Another photo from the summer camp + +
    +
    + +

    Outline

    + +
    + +

    Day 1 (Monday, Aug. 4)

    +
      +
    • Welcome and introductions (All)
      • +
    • Day 1 (John, Glen, Adam)
      • +
        +
      • Background
        • +
          +
        • Basics of an IP Router
          • +
        • The NetFPGA hardware
          • +
        • How people use the NetFPGA
          • +
        • Why people use the NetFPGA
          • +
        +
      • The Stanford Base Reference Router
        • +
          +
        • Inside the NetFPGA hardware
          • +
        • Introduction to FPGAs and Verilog
          • +
        +
      • The Enhanced Reference Router
        • +
          +
        • Buffer sizing requirements in a router
          • +
        • Observering and controlling the queue size
          • +
        +
      • Life of a packet through the NetFPGA
        • +
          +
        • Data and control planes
          • +
        • Interface to software: Exceptions and Host I/O
          • +
        +
      • Address Lookup
        • +
      • PW-OSPF
        • +
      • Java-based Graphical User Interface (GUI)
        • +
      • Demonstration of High Definition (HD) video streaming
        • +
      +
    • Pizza dinner: AT&T Patio of the Gates Building
      • +
    +

    Day 2 (Tuesday, Aug. 5)

    +
      +
    • Module Development and Testing
      • +
        +
      • Running ModelSim with the NetFPGA TestBench (Glen)
        • +
          +
        • Compile, simulate, view waveforms
          • +
        • Example: Simply Encryption on a packet payload
          • +
        • Scrambling the payload with XOR using a key from a register
          • +
        +
      • Regression testing to verify hardware functionality (Adam)
        • +
          +
        • Synthesize and run the hardware
          • +
        • Verify value: 0xFFFFFFFF (would invert every bit of every byte of payload)
          • +
        • Verify value: 0xFF00FF00 (would invert every other byte of payload)
          • +
        • Verify value: 0x55555555 (would invert every other bit of payload)
          • +
        +
      +
    • Introduction to OpenFlow (Jad)
      • +
        +
      • Show how to use and test OpenFlow
        • +
      • Describe implementation of OpenFlow
        • +
      • Show use OpenFlow LiveCD
        • +
      • Give example of LiveCD on nf-test machines
        • +
      +
    • Group Dinner at MacArthur Park
      • +
    +

    Day 3 (Wednesday, Aug. 6)

    +
      +
    • Group Discussion
      • +
        +
      • Projects ideas
        • +
      • Scope of work that can be accomplished in 2-3 days
        • +
      +
    • Team up for Projects
      • +
        +
      • Project leaders will describe projects
        • +
      • Group will provide feedback on the scope
        • +
      • Be sure to have one hardware designer per team
        • +
      +
    • Precise Time Protocol (PTP) (Sara)
      • +
        +
      • Background and review of block diagrams
        • +
      • Show PTP running on nf-test machines
        • +
      • Show synchronization of pairs of machines
        • +
      • Discuss relevent Verilog Code
        • +
      +
    +

    Day 4 (Thursday, Aug. 7)

    +
      +
    • Work on Projects
      • +
        +
      • 802.1q VLANs
        • +
          +
        • Steve Padgett, Bilal Anwer, David Miller, Ke Xiang, Carson Stuart, Michael Blodgett
          • +
        • Top-Project Award
          • +
        +
      • Hardware-Accelerated Mathematics Library for NetFPGA
        • +
          +
        • Dan Bedard, Will Tetteh, Yufeng Xin
          • +
        • Top-Project Award
          • +
        +
      • MACinMAC
        • +
          +
        • Jim Chen, Tatsuya Yabe, Hao Chen
          • +
        +
      • Heavy Hitter Identification using Multistage filters
        • +
          +
        • Faisal Khan, Guan Yo, and Atif
          • +
        +
      • Layer 2 Load Balancing
        • +
          +
        • Danai Chasaki, Fernando Hammerli, Paul Germano
          • +
        +
      • TCP Traffic Analysis for Passive End-to-End Bandwidth Measurement
        • +
          +
        • Martin Zadnik, Yaping Zhu
          • +
        +
      • Assessment of Prototyping an AFDX Policy Switch Leveraging NetFPGA, Ethane, and OpenFlow Switch
        • +
          +
        • Tom Gaska
          • +
        +
      • ntop on NetFPGA
        • +
          +
        • Songkrant Muneenaem
          • +
        +
      • Universal Hash Function
        • +
          +
        • Thomas Zink and Dominik Schmucki
          • +
        +
      +
    • NetFPGA group available for Questions and Answers
      • +
    +

    Day 5 (Friday, Aug. 8)

    +
      +
    • Complete Projects
      • +
        +
      • On the SummerCamp_2008_Projects page, verify your project description and team members
        • +
          +
        • Update the link to your presentation page
          • +
        • Update the link to your contribute file page
          • +
        +
      • 10-minute project presentations
        • +
      • Live demonstrations
        • +
      +
    • Award prizes to winning projects
      • +
    • Group Dinner at California Cafe
      • +
    +

    Saturday, Aug. 9

    +
      +
    • Checkout of Stanford Guest House
      • +
    + +
    +
    + +

    Background Reading

    + +
    + + + +
    +
    + +

    To Attend this Event

    +
      +
    • Mark your calendar with the dates of the event
      • +
        +
      • Please plan to arrive Sunday night, August 3
        • +
      • Please plan to stay through Saturday morning, August 9
        • +
      • Registration fee covers shared meals (all breakfasts, lunches, and most dinners)
        • +
          +
        • Registration Fee: $400
          • +
        • Summer Camp is Full!! No more registrations can be accepted!
          • +
        +
      • A limited number of scholarships are available for students or instructors from schools unable to cover registration and hotel expenses.
        • +
          +
        • Award of the scholarships will be based on both merit and need:
          • +
        • Please provide one paragraph about that describes your relevant technical background in networking and/or hardware design.
          • +
        • Please provide another paragraph that explains why you or your host institution needs financial help.
          • +
        • Summer Camp is Full!! No more registrations can be accepted!
          • +
        +
      +
    • Travel Information
      • +
        +
      • Direct flights are available to most parts of the country through SFO or SJC
        • +
      • CalTrain offers fast transportation between the airports and Palo Alto
        • +
      • The Marguerite Shuttle offers rides between the train station, hotel, and campus. No car rental is needed.
        • +
      +
    • Book accomondations at the Stanford Guest House.
      • +
        +
      • Single rooms are $89/night
        • +
      • Shuttle service available to campus
        • +
      +
    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2008-08-17-SIGCOMM-2008-Tutorial.html b/_pages/2008-08-17-SIGCOMM-2008-Tutorial.html new file mode 100644 index 0000000..862fdfb --- /dev/null +++ b/_pages/2008-08-17-SIGCOMM-2008-Tutorial.html @@ -0,0 +1,303 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    SIGCOMM 2008 Tutorial

    + +
    +
    + +

    Building Gigabit-rate Routers with the NetFPGA at the SIGCOMM 2008 Conference

    + +
    + +

    Presented by: John W. Lockwood, Glen Gibb, and Adam Covington of the High Performance Network Group at Stanford University

    +

    Date: Sunday, August 17, 2008

    +

    Time: 9am - 5pm

    +

    Location: Laboratory/Classroom, Seattle, Washington, United States

    + +
    +
    + +

    Abstract

    + +

    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks. +

    + +

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

    + + +

    This full-day hands-on tutorial will be held in a classroom or laboratory equipped with ten PCs with NetFPGA hardware on Sunday or Monday, August 17 or 18, 2008.

    + +
    +
    + +

    Background

    + +

    Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at the Hot Interconnects tutorial and the SIGMETRICS tutorials in 2007.

    + +
    +
    + +

    Outline

    + +
    + +
      +
    • Introduction to the operation of an Internet Router
      • +
        +
      • Control Plane
        • +
          +
        • Routing protocols
          • +
        • Routing table
          • +
        • Management interfaces
          • +
        +
      • Datapath
        • +
          +
        • Longest Prefix Match (LPM)
          • +
        • Classless Interdomain Routing (CIDR)
          • +
        • Header processing
          • +
        • Packet buffering
          • +
        +
      +
    • The NetFPGA Router
      • +
        +
      • Hardware
        • +
          +
        • Gigabit Ethernet interfaces
          • +
        • Field Programmable Gate Array (FPGA) Logic
          • +
        • Random Access Memory (RAM)
          • +
        +
      • Software
        • +
          +
        • Kernel-space driver
          • +
        • User-space applications
          • +
        • PCI interface
          • +
        +
      +
    • Demonstration Topology
      • +
        +
          +
        • Hardware
          • +
            +
          • Network of ten routers
            • +
          • Ethernet switch
            • +
          • Video server
            • +
          • High Definition (HD) video client
            • +
          +
        • Software
          • +
            +
          • PW-OSPF
            • +
          • Routing tables
            • +
          • Dynamic re-routing
            • +
          +
        +
      +
    • Integrated Circuit Design
      • +
        +
      • Technologies
        • +
          +
        • Look-Up Tables (LUTs)
          • +
        • Configurable Logic Blocks (CLBs)
          • +
        • Field Programmable Gate Arrays (FPGAs)
          • +
        +
      • Verilog Hardware Description Language (HDL)
        • +
          +
        • Registers, integers, arrays
          • +
        • Multiplexers
          • +
        • Synchronous storage elements
          • +
        • Finite State Machines (FSMs)
          • +
        +
      • Hardware Debug
        • +
          +
        • Waveform monitor
          • +
        • In-circuit logic emulation
          • +
        +
      +
    • NetFPGA System Components
      • +
        +
      • Synthesis of tutorial router
        • +
      • Java-based Graphical User Interface (GUI)
        • +
          +
        • Configuration
          • +
        • Statistics
          • +
        +
      • Router Architecture
        • +
          +
        • Pipeline
          • +
        • Queues
          • +
        +
      +
    • Buffer Size Experiment
      • +
        +
      • Experiment with TCP/IP flows
        • +
          +
        • Rule-of-thumb for the buffer size
          • +
        • Round-trip propation delay
          • +
        • Capacity of bottlneck link
          • +
        • Number of active flows
          • +
        +
      • Lower delay with smaller queues
        • +
      +
    • Enhanced Router
      • +
        +
      • Additional hardware
        • +
          +
        • Event capture module
          • +
        • Rate limiter
          • +
        • Delay module
          • +
        +
      • Experiments
        • +
          +
        • Netperf
          • +
        • HD video transport
          • +
        +
      • Life of packet through the system
        • +
          +
        • Description of blocks
          • +
        • Waveforms
          • +
        +
      +
    + +
    +
    + +

    About the presentors

    + +
    + +
      +
    • John W. Lockwood
      John W. Lockwood is a Consulting Associate Professor at Stanford University. At Stanford, he leads the NetFPGA Alpha and Beta release programs and organizes the worldwide tutorial program. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology. Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies. Dr. Lockwood earned his Ph.D from the Department of Electrical and Computer Engineering at the University of Illinois.

      John Lockwood has served as the principal investigator on grants from the National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.
      • +
      +
    • Glen Gibb
      Glen is a PhD candidate in Electrical Engineering at Stanford University. He received his Master of Science in Electrical Engineering from Stanford University and a Bachelor of Science and a Bachelor of Engineering from The University of Melbourne in Australia. He has been working on the NetFPGA platform since 2004 and was the lead designer for the current hardware version.
      • +
      +
    • Adam Covington
      Adam is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. He is currently working on the NetFPGA project, which enables researchers and instructors to build hardware-accelerated networking systems. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. While at Washington University he designed, and implemented clustering algorithms on FPGAs and supported a hardware accelerated classification system on the FPX platform. Adam’s current research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Adam completed a Bachelor of Science degree in Computer Engineering from Western Michigan University in April 2003 and accepted a Distinguished Masters of Science Fellowship from Washington University. He completed his Masters of Science degree in Computer Science and Engineering from Washington University in December 2006. Adam continues to provide support for the NetFPGA project which includes helping users worldwide as well as arranging and presenting tutorials.
      • +
    + +
    +
    + +

          Schedule
    9:00-10:30 tutorial session
    10:30-11:00 coffee break
    11:00-12:30 tutorial session
    12:30-1:30 lunch
    1:30-3:00 tutorial session
    3:00-3:30 coffee break
    3:30-5:30 tutorial session

    + +
    +
    + +

    To Register

    + +
    + +

    Register directly with SIGCOMM to attend the conference and/or the NetFPGA workshop.

    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2009-08-13-NetFPGA-Developers-Worshop-2009.html b/_pages/2009-08-13-NetFPGA-Developers-Worshop-2009.html new file mode 100644 index 0000000..6b6b17e --- /dev/null +++ b/_pages/2009-08-13-NetFPGA-Developers-Worshop-2009.html @@ -0,0 +1,188 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA Developers Workshop 2009

    + +
    +
    + +

    You already know that the NetFPGA implements a Gigabit NIC, A hardware-accelerated Internet router, a traffic generator, and an OpenFlow switch, and more. What else can it do? We invite you, our NetFPGA Developers, to join us at Stanford to see the newest NetFPGA Modules. Attend the workshop to see presentations and demonstrations of the latest network hardware and software.

    + +
    + +A NetFPGA Board with a list of what projects going into it highlighting that one can add their own + +
    + +
      +
    • Workshop Dates:
      • +
        +
      • Demonstration Setup (for authors): Aug. 12, 2009
        • +
      • Workshop Presentations & Demonstrations: Aug. 13-14, 2009
        • +
      • Full Proceedings
        • +
      • Agenda
        • +
      • Papers Due: Apr. 27, 2009
        • +
      +
    • Location
      • + +
    • Presentations and Demonstrations on
      • +
        +
      • Hardware enhancements for packet forwarding
        • +
      • Hardware applications for payload scanning
        • +
      • Methodology for high-level programming networking hardware
        • +
      • Testbed deployments
        • +
      • Data-plane virtualization
        • +
      • Applications that support soft radio, and traffic generation
        • +
      • More. See draft program on Wiki
        • +
      +
    • Event Registration To cover Breakfasts, Snacks, Lunch, and Dinner
      • +
        +
      • Early Registration: Before July 14
        • +
      • Late Registration: After July 14
        • +
      +
    • Hotel: Sheraton Palo Alto
      • +
        +
      • Rooms at $169/Night available using code NETFPGA
        • +
      • Check-in on: Tue. Aug 11 -- Checkout Fri, Aug 14 or Sat. Aug 15.
        • +
      +
    • Transportation
      • +
        +
      • Nearby Airports: San Francisco (SFO) and San Jose (SJC)
        • +
      • Marguerite: Free Shuttle Service on Stanford Campus
        • +
      • CalTrain: Green alternative to renting a car
        • +
      +
    • Program Chairs
      • +
        +
      • John Lockwood: Stanford University
        • +
      • Andrew W. Moore: Cambridge University
        • +
      +
    • Program Committee
      • +
        +
      • Satnam Singh, Microsoft Research Cambridge
        • +
      • David Miller, Cambridge University Computer Laboratory
        • +
      • Gordon Brebner, Xilinx
        • +
      • Martin Žádník, Brno University of Technology
        • +
      • Glen Gibb: Stanford University
        • +
      • Adam Covington: Stanford University
        • +
      • David Greaves: Cambridge University
        • +
      • Eric Keller: Princeton University
        • +
      +
    • Single-page Call for Papers posting
      • +
    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2010-03-21-IETF-Tutorial-2010-Anaheim.html b/_pages/2010-03-21-IETF-Tutorial-2010-Anaheim.html new file mode 100644 index 0000000..1ab1f32 --- /dev/null +++ b/_pages/2010-03-21-IETF-Tutorial-2010-Anaheim.html @@ -0,0 +1,292 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    IETF Tutorial 2010 (Anaheim)

    + +
    +
    + +

    Hands-on with the NetFPGA to build a Gigabit-rate Router

    + +
    + +

    Presented by: G. Adam Covington, James Zheng of the High Performance Network Group at Stanford University

    +

    Date: Sunday, March 21, 2010

    +

    Time: 9am - 5pm

    +

    Location: Manhattan Room, Anaheim Hilton, Anaheim, California, United States

    + +
    +
    + +

    Abstract

    + +

    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

    +

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

    +

    This full-day hands-on tutorial will be held in a classroom or laboratory equipped with ten PCs with NetFPGA hardware on Sunday, March 21, 2010.

    + +
    +
    + +

    Background

    + +
    + +

    Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at previous NetFPGA Turorials from 2007-2009 (FPL 2009, SIGCOMM 2008, Hot Interconnects 2007, SIGMETRICS 2007). Information about previous events as well as a description of the NetFPGA Platform are available on-line from the NetFPGA homepage.

    + +
    +
    + +

    Outline

    + +
    + +
      +
    • Introduction to the operation of an Internet Router
      • +
        +
      • Control Plane
        • +
          +
        • Routing protocols
          • +
        • Routing table
          • +
        • Management interfaces
          • +
        +
      • Datapath
        • +
          +
        • Longest Prefix Match (LPM)
          • +
        • Classless Interdomain Routing (CIDR)
          • +
        • Header processing
          • +
        • Packet buffering
          • +
        +
      +
    • The NetFPGA Router
      • +
        +
      • Hardware
        • +
          +
        • Gigabit Ethernet interfaces
          • +
        • Field Programmable Gate Array (FPGA) Logic
          • +
        • Random Access Memory
          • +
        +
      • Software
        • +
          +
        • Kernel-space driver
          • +
        • User-space applications
          • +
        • PCI host interface
          • +
        +
      • System Configuration
        • +
      +
    • Demonstration Topology
      • +
        +
      • Hardware
        • +
          +
        • Network of ten routers
          • +
        • Ethernet switch
          • +
        • Video server
          • +
        • High Definition (HD) video client
          • +
        +
      • Software
        • +
          +
        • PW-OSPF
          • +
        • Routing tables
          • +
        • Dynamic re-routing
          • +
        +
      +
    • Integrated Circuit Design
      • +
        +
      • Technologies
        • +
          +
        • Look-Up Tables (LUTs)
          • +
        • Configurable Logic Blocks (CLBs)
          • +
        • Field Programmable Gate Arrays (FPGAs)
          • +
        +
      • Verilog Hardware Description Language (HDL)
        • +
          +
        • Registers, integers, arrays
          • +
        • Multiplexer
          • +
        • Synchronous storage elements
          • +
        • Finite State Machines (FSMs)
          • +
        +
      • Hardware Debug
        • +
          +
        • Waveform monitor
          • +
        • In-circuit logic emulation
          • +
        +
      +
    • NetFPGA System Components
      • +
        +
      • Synthesis of tutorial router
        • +
      • Java-based Graphical User Interface
        • +
          +
        • Configuration
          • +
        • Statistics
          • +
        +
      • Router Architecture
        • +
          +
        • Pipeline
          • +
        • Queues
          • +
        +
      +
    • Buffer Size Experiment
      • +
        +
      • Experiment with TCP/IP
        • +
          +
        • Rule-of-thumb for the buffer size
          • +
        • Round-trip propation delay
          • +
        • Capacity of bottlneck link
          • +
        +
      • Lower delay with smaller queues
        • +
      +
    • Enhanced Router
      • +
        +
      • Additional hardware
        • +
          +
        • Event capture module
          • +
        • Rate limiter
          • +
        • Delay module
          • +
        +
      • Experiments
        • +
          +
        • Netperf
          • +
        • HD video transport
          • +
        +
      • Life of packet through the system
        • +
          +
        • Description of blocks
          • +
        • Waveforms from logic anazlyzer
          • +
        +
      +
    + +
    +
    + +

    About the presentors

    +
      +
    • Adam Covington
      Adam is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. He is currently working on the NetFPGA project, which enables researchers and instructors to build hardware-accelerated networking systems. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. While at Washington University he designed, and implemented clustering algorithms on FPGAs and supported a hardware accelerated classification system on the FPX platform. Adam’s current research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Adam completed a Bachelor of Science degree in Computer Engineering from Western Michigan University in April 2003 and accepted a Distinguished Masters of Science Fellowship from Washington University. He completed his Masters of Science degree in Computer Science and Engineering from Washington University in December 2006. Adam continues to provide support for the NetFPGA project which includes helping users worldwide as well as arranging and presenting tutorials.
      • +
      +
    • James Hongyi Zeng
      James Hongyi Zeng received his Bachelor of Science degree in Electrical Engineering from Tsinghua University, China in 2008, with a concentration in wireless communication. He is currently pursuing a PhD degree in Electrical Engineering at Stanford University. His research mainly focuses on data center network, high performance router architecture, and software defined radio. He has been working on the NetFPGA platform since 2008 and is the core designer on the next generation NetFPGA 10G platform. James has previously worked in Microsoft Research Asia as a Visiting Student, where he worked on GPU-based soft WiFi project.
      • +
    + +
    +
    + +

          Schedule
    9:00-10:30 Tutorial Session
    10:30-11:00 Coffee Break
    11:00-12:30 Tutorial Session
    12:30-1:30 Lunch
    1:30-3:00 Tutorial Session
    3:00-3:30 Coffee Break
    4:00-5:30 Tutorial Session

    + +
    +
    + +

    Registration

    +
    +

    Cost of the tutorial is $200. Register here to attend

    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2010-07-02-NetFPGA-Summer-Camp-2010.html b/_pages/2010-07-02-NetFPGA-Summer-Camp-2010.html new file mode 100644 index 0000000..2195c5a --- /dev/null +++ b/_pages/2010-07-02-NetFPGA-Summer-Camp-2010.html @@ -0,0 +1,316 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA Summer Camp 2010

    + +
    +
    + +

    Build an Internet routers and learn about clean-slate switches at a 5-day summer camp held at Stanford University

    + +
    + +

    Presented by: the Stanford NetFPGA Group

    +

    Open to: Academics teaching with the NetFPGA, and researchers (postdoc or graduate-student) interested in develping new hardware-accelerated network applications

    +

    Date: Monday, August 9 - Friday, August 13, 2010

    +

    Time: 9am - 5pm. Evening events will be announced here

    +

    Location: The Stanford University campus located between San Francisco and San Jose in the heart of the Silicon Valley

    + +
    +
    + +

    Background

    + +
    + +

    This week-long summercamp extends the material presented at the shorter workshop events.

    + +
    +
    + +A photo from the summer camp + +
    +
    + +

    Outline

    + +
    + +

    Day 1 (Monday, Aug. 9)

    +
      +
    • Welcome and introductions
      • +
    • Day 1
      • +
        +
      • Background
        • +
          +
        • Basics of an IP router
          • +
        • The NetFPGA hardware
          • +
        • How people use the NetFPGA
          • +
        • Why people use NetFPGA
          • +
        +
      • The Stanford Base Reference Router
        • +
          +
        • Inside the NetFPGA hardware
          • +
        • Introduction to FPGAs and Verilog
          • +
        +
      • The Enhanced Reference Router
        • +
          +
        • Buffer sizing requirements in a router
          • +
        • Observering and controlling the queue size
          • +
        +
      • Life of a packet through the NetFPGA
        • +
          +
        • Data and control planes
          • +
        • Interface to software: Exceptions and Host I/O
          • +
        +
      • Demonstration of the NetFPGA
        • +
          +
        • Address Lookup
          • +
        • PW-OSPF
          • +
        • Java-based Graphical User Interface (GUI)
          • +
        • Demonstration of High Definition (HD) video streaming
          • +
        +
      • Slides: Will be available here
        • +
      +
    +

    Day 2 (Tuesday, Aug. 10)

    +
      +
    • Module Development and Testing
      • +
        +
      • Running Model Sim with the NetFPGA TestBench
        • +
          +
        • Compile, simulate, view waveforms
          • +
        • Example: Simply Encryption on a packet payload
          • +
        • Scrambling the payload with XOR using a key from a register
          • +
        +
      • Regression testing to verify hardware functionality
        • +
          +
        • Synthesize and run the hardware
          • +
        • Verify value: 0xFFFFFFFF (would invert every bit of every byte of payload)
          • +
        • Verify value: 0xFF00FF00 (would invert every other byte of payload)
          • +
        • Verify value: 0x55555555 (would invert every other bit of payload)
          • +
        +
      • Slides: Will be available here
        • +
      +
    • Group discussion
      • +
        +
      • Projects ideas
        • +
      • Scope of work that can be accomplished in 2-3 days
        • +
      +
    • Team up for Projects
      • +
        +
      • Project leaders will describe projects
        • +
      • Group will provide feedback on the scope
        • +
      • Be sure to have one hardware designer per team
        • +
      +
    • Example Hardware Design
      • +
        +
      • Background and review of block diagrams
        • +
      • Show design running on nf-test machines
        • +
      • Discuss relevant Verilog Code
        • +
      +
    +

    Day 3 (Wednesday, Aug. 11)

    +
      +
    • Work on Projects, examples from Summerschool 2010
      • +
        +
      • 802.1q VLANs
        • +
      • Hardware-Accelerated Mathematics Library for NetFPGA
        • +
      • MACinMAC
        • +
      • Heavy Hitter Identification using Multistage filters
        • +
      • Layer 2 Load Balancing
        • +
      • Pattern Matching/Mini-IDS
        • +
      • TCP Traffic Analysis for Passive End-to-End Bandwidth Measurement
        • +
      • Assessment of Prototyping an ADFX Policy Switch Leveraging NetFPGA, Ethane, and OpenFlow Switch
        • +
      • ntop on NetFPGA
        • +
      • Universal Hash Function
        • +
      +
    • NetFPGA group available for Questions and Answers
      • +
    • Dinner: Pizza in the Fijitsu Lounge, Gates Building, 6pm
      • +
    +

    Day 4 (Thursday, Aug. 12)

    +
      +
    • Complete Projects
      • +
    • 10-minute project presentations.
      • +
    • Live demonstrations
      • +
    • Award prizes to winning projects
      • +
    +

    Day 5 (Friday, Aug. 13)

    +
      +
    • NetFPGA Developers Conference
      • +
    • Dinner: MacArthur Park 7pm
      • +
    +

    Saturday, Aug. 14

    +
      +
    • Checkout of Stanford Guest House
      • +
    + +
    +
    + +

    Background Reading

    + +
    + + + +
    +
    + +

    To Attend this Event

    + +
    + +
      +
    • Mark your calendar with the dates of the event
      • +
        +
      • Please plan to arrive Sunday night, August 8
        • +
      • Please plan to stay through Saturday morning, August 14
        • +
      • Registration fee covers shared meals (all breakfasts, lunches, and most dinners)
        • +
          +
        • Registration Fee: $450
          • +
        • Register: Registration Site
          • +
        • Registration Deadline: June 15th
          • +
        +
      • A limited number of scholarships are available for students or instructions from schools unable to cover registration and hotel expenses. Scholarship applicants do not need to register through the registration website
        • +
          +
        • Award of the scholarships will be based on both merit and need:
          • +
        • Please provide one paragraph about that describes your relevant technical background in networking and/or hardware design
          • +
        • Please provide another paragraph that explains why you or your host institution needs financial help.
          • +
        • Scholarship Application:
          • +
        +
      +
    • Travel Information
      • +
        +
      • Direct flights are available to most parts of the country through SFO or SJC
        • +
      • CalTrain offers fast transportation between the airports and Palo Alto
        • +
      • The Marguerite Shuttle offers rides between the train station, hotel and campus. No car rental is needed.
        • +
      +
    • Book accommodations at the Stanford Guest House.
      • +
        +
      • There are a block of rooms reserved for the NetFPGA event
        • +
      • These rooms are only guaranteed to be available until 06/29/2010
        • +
      • To reserve rooms call: (650) 926-2800 with the reservation code 'NetFPGA'
        • +
      • Single rooms are $109/night
        • +
      • Double rooms are $139/night
        • +
      • Shuttle services available to campus
        • +
      +
    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2010-09-12-2nd-North-American-NetFPGA-Developers-Workshop.html b/_pages/2010-09-12-2nd-North-American-NetFPGA-Developers-Workshop.html new file mode 100644 index 0000000..ac74a7c --- /dev/null +++ b/_pages/2010-09-12-2nd-North-American-NetFPGA-Developers-Workshop.html @@ -0,0 +1,183 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    2nd North American NetFPGA Developers Workshop 2010

    + +
    +
    + +

    You already know that the NetFPGA implements a Gigabit NIC, A hardware-accelerated Internet router, a traffic generator, and an OpenFlow switch, and more. What else can it do? We invite you, our NetFPGA Developers, to join us at Stanford to see the newest NetFPGA Modules. Attend the workshop to see presentations and demonstrations of the latest network hardware and software.

    + +
    + +A NetFPGA Board with a list of what projects going into it highlighting that one can add their own + +
    + +
      +
    • Agenda: Schedule
      • +
    • Workshop Dates:
      • +
        +
      • Demonstration Setup (for authors): Aug. 12, 2010
        • +
      • Workshop Presentation & Demonstrations: Aug. 13, 2010
        • +
      • Papers Due: Monday 14 Jun 2010 6:00:00pm PDT
        • +
      +
    • Location
      • + +
    • Event Registration To cover Breakfasts, Snacks, Lunch, and Dinner
      • +
        +
      • Early Registration: Before July 14
        • +
      • Late Registration: After July 14
        • +
      • Registration Site
        • +
      +
    • Hotel: Stanford Guest House
      • +
        +
      • Rooms at $109/night
        • +
      +
    • Transportation
      • +
        +
      • Nearby Airports: San Francisco (SFO) and San Jose (SJC)
        • +
      • Marguerite: Free Shuttle Service on Stanford Campus
        • +
      • CalTrain: Green alternative to renting a car
        • +
      +
    • General/Organizing Chair
      • +
        +
      • G. Adam Covington, Stanford University
        • +
      +
    • Program Chairs
      • +
        +
      • Yashar Ganjali, University of Toronto
        • +
      • Andrew W. Moore, Cambridge University
        • +
      +
    • Program Committee
      • +
        +
      • Satnam Singh, Microsoft Research Cambridge
        • +
      • Paul Rodman, Google
        • +
      • Gordon Brebner, Xilinx
        • +
      • Martin Žádník, Brno University of Technology
        • +
      • Glen Gibb, Stanford University
        • +
      • James Zheng, Stanford University
        • +
      • Scott Whyte, Google
        • +
      • Eric Keller, Princeton University
        • +
      • Jad Naous, Stanford University
        • +
      • Greg Steffen, University of Toronto
        • +
      • John Lockwood, Algo-Logic Systems
        • +
      • Sun Moon, KAIST
        • +
      +
    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2011-08-01-NetFPGA-Summer-Camp-2011.html b/_pages/2011-08-01-NetFPGA-Summer-Camp-2011.html new file mode 100644 index 0000000..1223a94 --- /dev/null +++ b/_pages/2011-08-01-NetFPGA-Summer-Camp-2011.html @@ -0,0 +1,342 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

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    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA Summer Camp 2011

    + +
    +
    + +

    Build an Internet routers and learn about clean-slate switches at a 5-day summer camp held at Stanford University

    + +
    + +

    Presented by: the Stanford NetFPGA Group.

    +

    Open to: Academics teaching classes with the NetFPGA, and researchers (postdoc or graduate-student) interested in developing new hardware-accelerated network applications.

    +

    Date: Monday, August 1 - Friday, August 5, 2011

    +

    Time: 9am - 5pm, Evening events will be announced here.

    +

    Location: The Stanford University campus located between San Francisco and San Jose in the heart of Silicon Valley.

    + +
    +
    + +

    Background

    + +
    + +

    This week-long summercamp extends the material presented at the shorter workshop events

    + +
    +
    + +A photo from the camp + +
    +
    + +Another photo from the camp + +
    +
    + +

    Outline

    + +
    + +

    Day 1 (Monday, July 30)

    +
      +
    • Welcome and introductions
      • +
    • NetFPGA
      • +
        +
      • Infrastructure
        • +
          +
        • Tree
          • +
        • Build System
          • +
        • Scripts
          • +
        +
      • Life of a packet through the NetFPGA
        • +
          +
        • Data and control planes
          • +
        • Interface to software: Execeptions and Host I/O
          • +
        +
      • Implementation
        • +
          +
        • Module Template
          • +
        • User Data Path
          • +
        • Write crypto NIC using a static key
          • +
        +
      • Simulation and Debug
        • +
          +
        • Simulation Functions
          • +
        • Write and Run Simulations for crypto NIC
          • +
        +
      +
    + +
    + +

    Day 2 (Tuesday, July 31)

    +
      +
    • NetFPGA (cont.)
      • +
        +
      • Registers
        • +
          +
        • Explain Register System
          • +
        • Add XML to define crypto NIC encryption key
          • +
        • Use Generic Register Module to implement register
          • +
        • Update Simulations
          • +
        +
      • Build and Test Hardware
        • +
          +
        • Build
          • +
        • Explanation of Hardware Tests
          • +
        • Write and run Hardware Tests
          • +
            +
          • Verify value: 0xFFFFFFFF
            • +
          • Verify value: 0xFF00FF00
            • +
          • Verify value: 0x55555555
            • +
          +
        +
      • Writing Software and Integration
        • +
          +
        • Write setkey.c/getkey.c to write/read registers
          • +
        • Test between adjacent computers
          • +
        +
      +
    • Group Discussion
      • +
        +
      • Projects ideas
        • +
      • Scope of work that can be accomplished in 2-3 days
        • +
      +
    • Team up for Projects
      • +
        +
      • Project leaders will describe projects
        • +
      • Group will provide feedback on the scope
        • +
      • Be sure to have one hardware designer per team
        • +
      +
    • Example Hardware Design
      • +
        +
      • Background and review of block diagrams
        • +
      • Show design running on nf-test machines
        • +
      • Discuss relevant Verilog Code
        • +
      +
    + +
    + +

    Day 3 (Wednesday, Aug. 1)

    +
      +
    • Work on Projects, examples from Summer Camp 2008 & 2010
      • +
        +
      • 802.1q VLANs
        • +
      • Hardware-Accelerated Mathematics Library for NetFPGA
        • +
      • MACinMAC
        • +
      • Heavy Hitter Identification using Multistage
        • +
      • Layer 2 Load Balancing
        • +
      • Pattern Matching/Mini-IDS
        • +
      • TCP Traffic Analysis for Passive End-to-End Bandwidth Measurement
        • +
      • Assessment of Prototyping an AFDX Policy Switch Leveraging NetFPGA, Ethane, and OpenFlow Switch
        • +
      • ntop on NetFPGA
        • +
      • Universal Hash Function
        • +
      +
    • NetFPGA group available for Questions and Answers
      • +
    • Dinner: TBD
      • +
    + +
    + +

    Day 4 (Thursday, Aug. 2)

    +
      +
    • Complete Projects
      • +
    + +
    + +

    Day 5 (Friday, Aug. 3)

    +
      +
    • Complete Projects
      • +
    • 10-minute project presentations
      • +
    • Live demonstrations
      • +
    • Award prizes to winning projects
      • +
    • Dinner: TBD
      • +
    + +
    + +

    Saturday, Aug. 4

    +
      +
    • Checkout of Stanford Guest House
      • +
    + +
    +
    + +

    Background Reading

    + +
    + + + +
    +
    + +

    To Attend this Event

    + +
    + +
      +
    • Mark your calendar with the dates of the event
      • +
        +
      • Please plan to arrive Sunday night, July 31
        • +
      • Please plan to stay through Saturday morning, August 6
        • +
      • Registration fee covers shared meals (all breakfasts, lunches, and most dinners)
        • +
          +
        • Registration Fee:
          • +
            +
          • Early (before June 15th): $250
            • +
          • Late (after June 15th): $350
            • +
          +
        • Register: Registration Site
          • +
        • Registration Deadline: June 15th
          • +
        +
      • A limited number of scholarships are available for students or instructors from schools unable to cover registration and hotel expenses. Scholarship applicants do not need to to register through the registration website.
        • +
          +
        • Award of the scholarships will be based on both merit and need:
          • +
        • Please provide one paragraph about that describes your relevant technical background in networking and/or hardware design.
          • +
        • Please provide another paragraph that explains why you or your host institution needs financial help.
          • +
        • Scholarship Application:
          • +
        +
      +
    • Travel Information
      • +
        +
      • Direct flights are available to most parts of the country through SFO and SJC
        • +
      • CalTrain offers fast transportation between the airports and the Palo Alto
        • +
      • The Marguerite Shuttle offers rides between the train station, hotel, and campus. No car rental is needed.
        • +
      +
    • Book accomodations at the Stanford Guest House
      • +
        +
      • There are a block of rooms reserved for the NetFPGA event
        • +
      • These rooms are only guaranteed to be available until 06/16/2011
        • +
      • To reserve rooms call: (650) 926-2800 with the reservation code 'NetFPGA'
        • +
      • Single rooms are $119/night
        • +
      • Shuttle services available to campus
        • +
      +
    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2011-08-19-Toronto-Tutorial-2011.html b/_pages/2011-08-19-Toronto-Tutorial-2011.html new file mode 100644 index 0000000..5e74f4a --- /dev/null +++ b/_pages/2011-08-19-Toronto-Tutorial-2011.html @@ -0,0 +1,239 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    Toronto Tutorial 2011 (Near SIGCOMM)

    + +
    +
    + +

    Informational Tutorial

    + +
    + +

    Presented by: Andrew W. Moore, G. Adam Covington

    +

    Date: Friday, August 19, 2011

    +

    Time: 8am - 12pm

    +

    Location: Pier 2/3 3rd floor, Westin Harbour Castle, Toronto, Canada

    + +
    +
    + +

    Abstract

    + +
    + +

    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

    +
    +

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

    +
    +NetFPGA Tutorial photo + +
    +
    + +

    Outline

    + +
    + +
      +
    • Introduction to platform
      • +
        +
      • Users (Professors & Researchers)
        • +
      • What is the NetFPGA
        • +
          +
        • Board
          • +
        • Tools & Reference Designs
          • +
        • Contributed
          • +
        • Community
          • +
        +
      +
    • Hardware Overview
      • +
        +
      • NetFPGA 1G
        • +
          +
        • Gigabit Ethernet interfaces
          • +
        • Field Programmable Gate Array (FPGA) Logic
          • +
        • Random Access Memory (RAM)
          • +
        • PCI interface
          • +
        +
      • NetFPGA 10G
        • +
          +
        • SPF+ interfaces
          • +
        • Field Programmable Gate Array (FPGA) Logic
          • +
        • Random Access Memory (RAM)
          • +
        • PCIe interface
          • +
        +
      +
    • Brief recap if IP/Routing
      • +
    • Example 1: Basic Functionality (reference router)
      • +
        +
      • PW-OSPF
        • +
      • Routing Tables
        • +
      • Dynamic re-routing
        • +
      +
    • Example 2: Advanced Functionality (buffer sizing based on reference router)
      • +
        +
      • Brief introduction of buffer sizing
        • +
          +
        • Rule-of-thumb for the buffer size
          • +
        • Round-trip propation delay
          • +
        • Capacity of bottlneck link
          • +
        • Number of active flows
          • +
        +
      • Additional Hardware
        • +
          +
        • Event capture module
          • +
        • Rate limiter
          • +
        • Delay module
          • +
        +
      • Experiments
        • +
          +
        • Netperf
          • +
        • HD video transport
          • +
        +
      +
    +

    Where to get started

    +
      +
    • Webpage
      • +
    • Wiki
      • +
    • Forums
      • +
    + +
    +
    + +

    About the presentors

    +
      +
    • Andrew W. Moore
      Andrew W. Moore is a Lecturer at the University of Cambridge Computer Laboratory. He joined the permanent faculty of Cambridge in 2007, prior to this he had been an EPSRC Roberts Fellow at Queen Mary, University of London, an Intel Research Fellow in Cambridge and foundation-researcher at the Cambridge Marconi research laboratory. Throughout this time Andrew has focused upon network characterisation and measurement, extensible monitoring for application performance-analysis and large-scale Internet monitoring and emulation. Interest in switch design has led to work in physical line-coding for optical networks, and novel optical-switch architectures.

      Andrew completed his Ph.D. with the Cambridge University Computer Laboratory in 2001 and prior to that took a Masters degree and an honours degree from Monash University in Melbourne. Australia. Alongside routine collaboration with AT&T, Endace, Intel, and Microsoft, Andrew Moore has served as principal investigator on grants from the UK Research Council (EPSRC) and a number of UK government bodies. He is a chartered engineer with the IET and a member of the IEEE, ACM and USENIX.
      • +
      +
    • Adam Covington
      Adam is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. He is currently working on the NetFPGA project, which enables researchers and instructors to build hardware-accelerated networking systems. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. While at Washington University he designed, and implemented clustering algorithms on FPGAs and supported a hardware accelerated classification system on the FPX platform. Adam’s current research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Adam completed a Bachelor of Science degree in Computer Engineering from Western Michigan University in April 2003 and accepted a Distinguished Masters of Science Fellowship from Washington University. He completed his Masters of Science degree in Computer Science and Engineering from Washington University in December 2006. Adam continues to provide support for the NetFPGA project which includes helping users worldwide as well as arranging and presenting tutorials.
      • +
    + +
    +
    + +

          Schedule
    8:00-10:00 tutorial session
    10:00-10:30 coffee break
    10:30-12:00 tutorial session

    + +
    +
    + +

    Registration

    + +
    + +

    Cost of the tutorial is $150. Register here to attend

    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2011-12-05-Tokyo-Tutorial-2011.html b/_pages/2011-12-05-Tokyo-Tutorial-2011.html new file mode 100644 index 0000000..9068f58 --- /dev/null +++ b/_pages/2011-12-05-Tokyo-Tutorial-2011.html @@ -0,0 +1,249 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    Tokyo Tutorial 2011 (Near CoNext)

    + +
    +
    + +

    Informational Tutorial

    + +
    + +

    Presented by: G. Adam Covington, Tatsuya Yabe

    +

    Date: Monday, December 5, 2011

    +

    Time: 1pm - 5pm

    +

    Location: IIJ (Internet Initiative Japan) Seminar room #2, 17th floor Jinbocho Mitsui Bldg., 1-105 Kanda Jinbo-cho, Chiyoda-ku, Tokyo, 101-0051, Japan

    + +
    +
    + +

    Abstract

    + +
    + +

    The NetFPGA is a open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Protocol (IP) routers using hardware rather than software. The platform can be used by researchers to protype advanced services for next-generation networks

    +
    +

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, attendees will learn about the NetFPGA platform and and how it can be used. We will demonstrate the use of the reference router to dynamically re-route traffic using PW-OSPF with streaming video traffic. We will also show how we can extend existing designs to experiment with buffer sizes.

    +
    +

    No knowledge of Verilog/VHDL is required to attend the tutorial, although knowledge of these languages is needed to program NetFPGA.

    +
    +
    +

    Outline

    +
      +
    • Introduction to the Platform
      • +
        +
      • Users (Professors & Researchers)
        • +
      • What is the NetFPGA
        • +
          +
        • Board
          • +
        • Tools & Reference Designs
          • +
        • Contributed Projects
          • +
        • Community
          • +
        +
      +
    • Hardware Overview
      • +
        +
      • NetFPGA 1G
        • +
          +
        • Gigabit Ethernet interfaces
          • +
        • Field Programmable Gate Array (FPGA) Logic
          • +
        • Random Access Memory (RAM)
          • +
        • PCI interface
          • +
        +
      • NetFPGA 10G
        • +
          +
        • SPF+ interfaces
          • +
        • Field Programmable Gate Array (FPGA) Logic
          • +
        • Random Access Memory (RAM)
          • +
        • PCIe interface
          • +
        +
      +
    • Brief recap if IP/Routing
      • +
    • Example 1: Basic Functionality (reference router)
      • +
        +
      • PW-OSPF
        • +
      • Routing Tables
        • +
      • Dynamic re-routing
        • +
      +
    • Example 2: Advanced functionality
      • +
        +
      • Brief introduction of buffer sizing
        • +
          +
        • Rule-of-thumb for the buffer size
          • +
        • Round-trip propation delay
          • +
        • Capacity of bottlneck link
          • +
        • Number of active flows
          • +
        +
      • Additional hardware
        • +
          +
        • Event capture module
          • +
        • Rate limiter
          • +
        +
      • Experiments
        • +
          +
        • Netperf
          • +
        • HD video transport
          • +
        +
      +
    + +

    Where to get started/What to do next

    +
      +
    • Webpage
      • +
    • Wiki
      • +
    • Forums
      • +
    + +
    +
    + +

    About the presenters

    + +
    + +
      +
    • Adam Covington
      Adam is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. he is currently working on the NetFPGA project, which enables researchers and instructors to build hardware-accelerated network systems. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. While at Washington University he designed, and implemented clustering algorithms on FPGAs and supported a hardware accelerated classification system on the FPX platform. Adam's current research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Adam completed a Bachelor of Science degree in Computer Engineering from Western Michigan University in April 2003 and accepted a Distinguished Masters of Science Fellowship from Washington University. He completed his Masters of Science degree in Computer Science and Engineering from Washington University in December 2006. Adam continues to provide support for the NetFPGA project which includes helping users worldwide as well as arranging and presenting tutorials.
      • +
      +
    • Tatsuya Yabe
      Tatsuya Yabe is a visiting researcher of the High-Performance Network Group (HPN) at Stanford University. He joined the group in 2008, and since he has been closely working with the NetFPGA development team. He also is an Assistant Manager of System Platforms Research Labs in NEC. Previously he was a hardware engineer in NEC Communication Systems. There, he successfully designed over a dozen FPGAs as well as circuit boards for large telecommunication carriers. He now owns several NetFPGA projects including OpenFlow implementation. He assisted the NetFPGA Summer Camp in 2010 and 2011.
      • +
    + +
    + +

          Schedule
    1:00-3:00 tutorial session
    3:00-3:30 coffee break
    3:30-5:00 tutorial session

    + +
    +
    + +

    Registration

    + +
    + +

    Before November 7, 2011:

    +
      +
    • Student $100
      • +
    • Attendee $200
      • +
    +

    November 7, 2011 and after

    +
      +
    • Student $150
      • +
    • Attendee $250
      • +
    + +
    + +

    Students must email a copy of their Student ID to gocoving@stanford.edu:
    Register here to attend

    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2012-07-30-NetFPGA-Summer-Camp-2012.html b/_pages/2012-07-30-NetFPGA-Summer-Camp-2012.html new file mode 100644 index 0000000..51df57d --- /dev/null +++ b/_pages/2012-07-30-NetFPGA-Summer-Camp-2012.html @@ -0,0 +1,349 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA Summer Camp 2012

    + +
    +
    + +

    Build an Internet routers and learn about clean-slate switches at a 5-day Summer Camp held at Stanford University

    + +
    + +

    Presented by: the Stanford NetFPGA Group

    +

    Open to: Academics teaching classes with the NetFPGA, and researchers (postdoc or graduate-students) interested in developing new hardware-accelerated network applications

    +

    Dates: Monday, July 30 - Friday, August 2012

    +

    Time: 9am - 5pm

    +

    Location: Center for Nanoscale Science and Engineering, Room 232, 348 Via Pueblo Stanford, CA, 94305

    +

    Survey: Survey Form

    + +
    +
    + +

    Background

    + +
    + +

    This week-long summercamp extends the material presented at the shorter workshop events

    + +
    +
    + +A photo from the camp + +
    +
    + +Another photo from the camp + +
    +
    + +

    Slides

    +

    Day 1: ppt
    Day 2: ppt 10G_ppt

    + +
    +
    + +

    Outline

    + +
    + +

    Day 1 (Monday, July 30)

    +
      +
    • Welcome and introductions
      • +
    • NetFPGA
      • +
        +
      • Infrastructure
        • +
          +
        • Tree
          • +
        • Build System
          • +
        • Scripts
          • +
        +
      • Life of a packet through the NetFPGA
        • +
          +
        • Data and control planes
          • +
        • Interface to software: Execeptions and Host I/O
          • +
        +
      • Implementation
        • +
          +
        • Module Template
          • +
        • User Data Path
          • +
        • Write crypto NIC using a static key
          • +
        +
      • Simulation and Debug
        • +
          +
        • Simulation Functions
          • +
        • Write and Run Simulations for crypto NIC
          • +
        +
      +
    + +
    + +

    Day 2 (Tuesday, July 31)

    +
      +
    • NetFPGA (cont.)
      • +
        +
      • Registers
        • +
          +
        • Explain Register System
          • +
        • Add XML to define crypto NIC encryption key
          • +
        • Use Generic Register Module to implement register
          • +
        • Update Simulations
          • +
        +
      • Build and Test Hardware
        • +
          +
        • Build
          • +
        • Explanation of Hardware Tests
          • +
        • Write and run Hardware Tests
          • +
            +
          • Verify value: 0xFFFFFFFF
            • +
          • Verify value: 0xFF00FF00
            • +
          • Verify value: 0x55555555
            • +
          +
        +
      • Writing Software and Integration
        • +
          +
        • Write setkey.c/getkey.c to write/read registers
          • +
        • Test between adjacent computers
          • +
        +
      +
    • Group Discussion
      • +
        +
      • Projects ideas
        • +
      • Scope of work that can be accomplished in 2-3 days
        • +
      +
    • Team up for Projects
      • +
        +
      • Project leaders will describe projects
        • +
      • Group will provide feedback on the scope
        • +
      • Be sure to have one hardware designer per team
        • +
      +
    • Example Hardware Design
      • +
        +
      • Background and review of block diagrams
        • +
      • Show design running on nf-test machines
        • +
      • Discuss relevant Verilog Code
        • +
      +
    + +
    + +

    Day 3 (Wednesday, Aug. 1)

    +
      +
    • Work on Projects, examples from Summer Camp 2008 & 2010
      • +
        +
      • 802.1q VLANs
        • +
      • Hardware-Accelerated Mathematics Library for NetFPGA
        • +
      • MACinMAC
        • +
      • Heavy Hitter Identification using Multistage
        • +
      • Layer 2 Load Balancing
        • +
      • Pattern Matching/Mini-IDS
        • +
      • TCP Traffic Analysis for Passive End-to-End Bandwidth Measurement
        • +
      • Assessment of Prototyping an AFDX Policy Switch Leveraging NetFPGA, Ethane, and OpenFlow Switch
        • +
      • ntop on NetFPGA
        • +
      • Universal Hash Function
        • +
      +
    • NetFPGA group available for Questions and Answers
      • +
    • Dinner: TBD
      • +
    + +
    + +

    Day 4 (Thursday, Aug. 2)

    +
      +
    • Complete Projects
      • +
    + +
    + +

    Day 5 (Friday, Aug. 3)

    +
      +
    • Complete Projects
      • +
    • 10-minute project presentations
      • +
    • Live demonstrations
      • +
    • Award prizes to winning projects
      • +
    • Dinner: TBD
      • +
    + +
    + +

    Saturday, Aug. 4

    +
      +
    • Checkout of Stanford Guest House
      • +
    + +
    +
    + +

    Background Reading

    + +
    + + + +
    +
    + +

    To Attend this Event

    + +
    + +
      +
    • Mark your calendar with the dates of the event
      • +
        +
      • Please plan to arrive Sunday night, July 29
        • +
      • Please plan to stay through Saturday morning, August 4
        • +
      • Registration fee covers shared meals (all breakfasts, lunches and most dinners)
        • +
          +
        • Registration fee
          • +
            +
          • Early (before June 15th): $250
            • +
          • Late (after June 15th): $350
            • +
          +
        • Register: Registration Site
          • +
        • Registration Deadline: July 6th
          • +
        +
      • A limited number of scholarships are available for students or instructors from schools unable to cover registration and hotel expenses. Scholarships applicants do not need to register through the registration website.
        • +
          +
        • Award of the scholarships will be based on both merit and need:
          • +
        • Please provide one paragraph about that describes your relevant technical background in networking and/or hardware design.
          • +
        • Please provide another paragraph that explains why you or your host institution needs financial help.
          • +
        • Scholarship Application:
          • +
        +
      +
    • Travel Information
      • +
        +
      • Direct flights are available to most parts of the country through SFO or SJC
        • +
      • CalTrain offers fast transportation between Airports and Palo Alto
        • +
      • The Marguerite Shuttle offers rides between the train station, hotel, and campus. No car rental is needed
        • +
      +
    • Book accomodations at the Stanford Guest House
      • +
        +
      • There are a block of rooms reserved for the NetFPGA event
        • +
      • These rooms are only guaranteed to be available until 06/16/2012
        • +
      • To reserve rooms, call (650) 926-2800 or online with the reservation code 'NetFPGA12'
        • +
      • Single rooms are $119/night
        • +
      • Shuttle services available to campus
        • +
      +
    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/_pages/2013-07-29-NetFPGA-Summer-Camp-2013-Stanford.html b/_pages/2013-07-29-NetFPGA-Summer-Camp-2013-Stanford.html new file mode 100644 index 0000000..a340013 --- /dev/null +++ b/_pages/2013-07-29-NetFPGA-Summer-Camp-2013-Stanford.html @@ -0,0 +1,347 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
    +
    +
    +
    +

    NetFPGA

    +
    +
    +
    +
    + + +
    +
    +
    +

    NetFPGA Summer Camp 2013

    + +
    +
    + +

    Build an internet router and learn about clean-slate switches at a 5-day summer camp held at Stanford University

    + +
    + +

    Open to: Academics teaching classes with the NetFPGA, and researchers (postdoc or graduate-student) interested in developing new hardware-accelerated network application

    +

    Location: Gates Building, Room 415, 353 Serra Mall, Stanford, CA 94305

    +

    Dates: Monday, July 29th - Friday, August 2 2012

    +

    Time: 9am - 5pm

    +

    Presented by: the Stanford NetFPGA Group.

    + +
    +
    + +

    Abstract

    + +
    + +

    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

    +

    By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

    + +
    +
    + +

    Background

    + +
    + +

    Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This week-long summercamp extends the material presented at the shorter workshop events.

    + +
    +
    + +A photo from the camp + +
    +
    + +Another photo from the camp + +
    +
    + +

    Slides

    + +
    + +

    Day 1: ppt

    + +
    +
    + +

    Outline

    + +
    + +

    Day 1 (Monday, July 29)

    +
      +
    • Welcome and Introductions
      • +
    • NetFPGA
      • +
        +
      • Infrastructure
        • +
          +
        • Tree
          • +
        • Build System
          • +
        • Scripts
          • +
        +
      • Life of a packet through the NetFPGA
        • +
          +
        • Data and control planes
          • +
        • Interface to software: Exceptions and Host I/O
          • +
        +
      • Implementation
        • +
          +
        • Module Template
          • +
        • User Data Path
          • +
        • Write crypto NIC using a static Key
          • +
        +
      • Simulation and Debug
        • +
          +
        • Simulation functions
          • +
        • Write and Run Simulations for crypto NIC
          • +
        +
      +
    + +
    + +

    Day 2 (Tuesday, July 30)

    +
      +
    • NetFPGA (cont.)
      • +
        +
      • Registers
        • +
          +
        • Explain Register System
          • +
        • Add XML to define crypto NIC encryption key
          • +
        • Use Generic Register Module to implement register
          • +
        • Update Simulations
          • +
        +
      • Build and Test Hardware
        • +
          +
        • Build
          • +
        • Explanation of Hardware Tests
          • +
        • Write and run Hardware Tests
          • +
            +
          • Verify value: 0xFFFFFFFF
            • +
          • Verify value: 0xFF00FF00
            • +
          • Verify value: 0x55555555
            • +
          +
        +
      • Writing Software and Integration
        • +
          +
        • Write setkey.c/getkey.c to write/read registers
          • +
        • Test between adjacent computers
          • +
        +
      +
    • Group Discussion
      • +
        +
      • Projects ideas
        • +
      • Scope of work that can be accomplished in 2-3 days
        • +
      +
    • Team up for Projects
      • +
        +
      • Project leaders will describe projects
        • +
      • Group will provide feedback on the scope
        • +
      • Be sure to have one hardware designer per team
        • +
      +
    • Example Hardware Design
      • +
        +
      • Background and review of block diagrams
        • +
      • Show design running on nf-test machines
        • +
      • Discuss relevant Verilog Code
        • +
      +
    + +
    + +

    Day 3 (Wednesday, July 31)

    +
      +
    • Work on Projects, examples from Summer Camp 2008 & 2010
      • +
        +
      • 802.1q VLANs
        • +
      • Hardware-Accelerated Mathematics Library for NetFPGA
        • +
      • MACinMAC
        • +
      • Heavy Hitter Identification using Multistage
        • +
      • Layer 2 Load Balancing
        • +
      • Pattern Matching/Mini-IDS
        • +
      • TCP Traffic Analysis for Passive End-to-End Bandwidth Measurement
        • +
      • Assessment of Prototyping an AFDX Policy Switch Leveraging NetFPGA, Ethane, and OpenFlow Switch
        • +
      • ntop on NetFPGA
        • +
      • Universal Hash Function
        • +
      +
    • NetFPGA group available for Questions and Answers
      • +
    • Dinner: TBD
      • +
    + +
    + +

    Day 4 (Thursday, Aug. 1)

    +
      +
    • Complete Projects
      • +
    + +
    + +

    Day 5 (Friday, Aug. 2)

    +
      +
    • Complete Projects
      • +
    • 10-minute project presentations
      • +
    • Live demonstrations
      • +
    • Award prizes to winning projects
      • +
    • Dinner: TBD
      • +
    + +
    +
    + +

    Background Reading

    + +
    + + + +
    +
    + +

    To Attend this Event

    + +
      +
    • Mark your calendar with the dates of the event
      • +
        +
      • Please plan to arrive Sunday night July 28
        • +
      • Please plan to stay through Saturday morning, August 3
        • +
      • Registration fee covers shared meals (all breakfasts, lunches, and most dinners)
        • +
          +
        • Registration Fee:
          • +
            +
          • Early (before June 15th): $250
            • +
          • Late (after June 15th): $350
            • +
          +
        • Register: Registration Site
          • +
        • Registration Deadline: July 6th
          • +
        +
      • A limited number of scholarships are available for students or instructors unable to cover registration and hotel expenses. Scholarship applicants do not need to register through the registration website.
        • +
          +
        • Award of the scholarships will be based on both merit and need:
          • +
        • Please provide one paragraph about that describes your relevant technical background in networking and/or hardware design.
          • +
        • Please provide another paragraph that explains why you or your host institution needs financial help.
          • +
        • Scholarship Application:
          • +
        +
      +
    • Travel Information
      • +
        +
      • Direct flights are available to most parts of the country through SFO and SJC
        • +
      • CalTrain offers fast transportation between the airports and Palo Alto
        • +
      • The Marguerite Shuttle offers rides between the train station, hotel, and campus. No car rental is needed.
        • +
      +
    • Hotel information coming soon
      • +
    + +
    +
    + +
    + + +
    +
    +
    +
    + NetFPGA +
    c/- Andrew W. Moore +
    William Gates Building
    JJ Thomson Avenue
    Cambridge.
    CB3 0FD +
    +
    +
    + P: + +44 1223 763500 +
    + E: + enquiries@netfpga.org +
    +
    + +

    Copyright © NetFPGA 2021

    +
    + +
    + + + + + + + + diff --git a/assets/css/main.css b/assets/css/main.css new file mode 100644 index 0000000..1454bf9 --- /dev/null +++ b/assets/css/main.css @@ -0,0 +1,3 @@ +:root{--blue: #007bff;--indigo: #6610f2;--purple: #6f42c1;--pink: #e83e8c;--red: #dc3545;--orange: #fd7e14;--yellow: #ffc107;--green: #28a745;--teal: #20c997;--cyan: #17a2b8;--white: #fff;--gray: #6c757d;--gray-dark: #343a40;--primary: #A3C1AD;--secondary: #6c757d;--success: #28a745;--info: #17a2b8;--warning: #ffc107;--danger: #dc3545;--light: #f8f9fa;--dark: #343a40;--breakpoint-xs: 0;--breakpoint-sm: 576px;--breakpoint-md: 768px;--breakpoint-lg: 992px;--breakpoint-xl: 1200px;--font-family-sans-serif: "Helvetica Neue", Arial, "Noto Sans", -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, sans-serif, "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Noto Color Emoji";--font-family-monospace: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", 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\"utf-8\";\n\n$primary: #A3C1AD;\n\n// Width of the content area\n$content-width: 800px;\n$on-palm: 600px;\n$on-laptop: 800px;\n\n// Use media queries like this:\n// @include media-query($on-palm) {\n// .wrapper {\n// padding-right: $spacing-unit / 2;\n// padding-left: $spacing-unit / 2;\n// }\n// }\n@mixin media-query($device) {\n @media screen and (max-width: $device) {\n @content;\n }\n}\n\n//@import \"bootstrap/bootstrap/bootstrap.css\";\n@import \"bootstrap/functions\";\n@import \"bootstrap/variables\";\n@import \"bootstrap/mixins\";\n@import \"bootstrap/root\";\n@import \"bootstrap/reboot\";\n@import \"bootstrap/type\";\n@import \"bootstrap/images\";\n@import \"bootstrap/code\";\n@import \"bootstrap/grid\";\n@import \"bootstrap/tables\";\n@import \"bootstrap/forms\";\n@import \"bootstrap/buttons\";\n@import \"bootstrap/transitions\";\n@import \"bootstrap/dropdown\";\n@import \"bootstrap/button-group\";\n@import \"bootstrap/input-group\";\n@import \"bootstrap/custom-forms\";\n@import \"bootstrap/nav\";\n@import \"bootstrap/navbar\";\n@import \"bootstrap/card\";\n@import \"bootstrap/breadcrumb\";\n@import \"bootstrap/pagination\";\n@import \"bootstrap/badge\";\n@import \"bootstrap/jumbotron\";\n@import \"bootstrap/alert\";\n@import \"bootstrap/progress\";\n@import \"bootstrap/media\";\n@import \"bootstrap/list-group\";\n@import \"bootstrap/close\";\n@import \"bootstrap/toasts\";\n@import \"bootstrap/modal\";\n@import \"bootstrap/tooltip\";\n@import \"bootstrap/popover\";\n@import \"bootstrap/carousel\";\n@import \"bootstrap/spinners\";\n@import \"bootstrap/utilities\";\n@import \"bootstrap/print\";\n\n@import \"style\", \"custom\";\n", + "// Bootstrap functions\n//\n// Utility mixins and functions for evaluating source code across our variables, maps, and mixins.\n\n// Ascending\n// Used to evaluate Sass maps like our grid breakpoints.\n@mixin _assert-ascending($map, $map-name) {\n $prev-key: null;\n $prev-num: null;\n @each $key, $num in $map {\n @if $prev-num == null or unit($num) == \"%\" {\n // Do nothing\n } @else if not comparable($prev-num, $num) {\n @warn \"Potentially invalid value for #{$map-name}: This map must be in ascending order, but key '#{$key}' has value #{$num} whose unit makes it incomparable to #{$prev-num}, the value of the previous key '#{$prev-key}' !\";\n } @else if $prev-num >= $num {\n @warn \"Invalid value for #{$map-name}: This map must be in ascending order, but key '#{$key}' has value #{$num} which isn't greater than #{$prev-num}, the value of the previous key '#{$prev-key}' !\";\n }\n $prev-key: $key;\n $prev-num: $num;\n }\n}\n\n// Starts at zero\n// Used to ensure the min-width of the lowest breakpoint starts at 0.\n@mixin _assert-starts-at-zero($map, $map-name: \"$grid-breakpoints\") {\n $values: map-values($map);\n $first-value: nth($values, 1);\n @if $first-value != 0 {\n @warn \"First breakpoint in #{$map-name} must start at 0, but starts at #{$first-value}.\";\n }\n}\n\n// Replace `$search` with `$replace` in `$string`\n// Used on our SVG icon backgrounds for custom forms.\n//\n// @author Hugo Giraudel\n// @param {String} $string - Initial string\n// @param {String} $search - Substring to replace\n// @param {String} $replace ('') - New value\n// @return {String} - Updated string\n@function str-replace($string, $search, $replace: \"\") {\n $index: str-index($string, $search);\n\n @if $index {\n @return str-slice($string, 1, $index - 1) + $replace + str-replace(str-slice($string, $index + str-length($search)), $search, $replace);\n }\n\n @return $string;\n}\n\n// Color contrast\n@function color-yiq($color, $dark: $yiq-text-dark, $light: $yiq-text-light) {\n $r: red($color);\n $g: green($color);\n $b: blue($color);\n\n $yiq: (($r * 299) + ($g * 587) + ($b * 114)) / 1000;\n\n @if ($yiq >= $yiq-contrasted-threshold) {\n @return $dark;\n } @else {\n @return $light;\n }\n}\n\n// Retrieve color Sass maps\n@function color($key: \"blue\") {\n @return map-get($colors, $key);\n}\n\n@function theme-color($key: \"primary\") {\n @return map-get($theme-colors, $key);\n}\n\n@function gray($key: \"100\") {\n @return map-get($grays, $key);\n}\n\n// Request a theme color level\n@function theme-color-level($color-name: \"primary\", $level: 0) {\n $color: theme-color($color-name);\n $color-base: if($level > 0, $black, $white);\n $level: abs($level);\n\n @return mix($color-base, $color, $level * $theme-color-interval);\n}\n", + "// Variables\n//\n// Variables should follow the `$component-state-property-size` formula for\n// consistent naming. Ex: $nav-link-disabled-color and $modal-content-box-shadow-xs.\n\n// Color system\n\n$white: #fff !default;\n$gray-100: #f8f9fa !default;\n$gray-200: #e9ecef !default;\n$gray-300: #dee2e6 !default;\n$gray-400: #ced4da !default;\n$gray-500: #adb5bd !default;\n$gray-600: #6c757d !default;\n$gray-700: #495057 !default;\n$gray-800: #343a40 !default;\n$gray-900: #212529 !default;\n$black: #000 !default;\n\n$grays: () !default;\n// stylelint-disable-next-line scss/dollar-variable-default\n$grays: map-merge(\n (\n \"100\": $gray-100,\n \"200\": $gray-200,\n \"300\": $gray-300,\n \"400\": $gray-400,\n \"500\": $gray-500,\n \"600\": $gray-600,\n \"700\": $gray-700,\n \"800\": $gray-800,\n \"900\": $gray-900\n ),\n $grays\n);\n\n$blue: #007bff !default;\n$indigo: #6610f2 !default;\n$purple: #6f42c1 !default;\n$pink: #e83e8c !default;\n$red: #dc3545 !default;\n$orange: #fd7e14 !default;\n$yellow: #ffc107 !default;\n$green: #28a745 !default;\n$teal: #20c997 !default;\n$cyan: #17a2b8 !default;\n\n$colors: () !default;\n// stylelint-disable-next-line scss/dollar-variable-default\n$colors: map-merge(\n (\n \"blue\": $blue,\n \"indigo\": $indigo,\n \"purple\": $purple,\n \"pink\": $pink,\n \"red\": $red,\n \"orange\": $orange,\n \"yellow\": $yellow,\n \"green\": $green,\n \"teal\": $teal,\n \"cyan\": $cyan,\n \"white\": $white,\n \"gray\": $gray-600,\n \"gray-dark\": $gray-800\n ),\n $colors\n);\n\n$primary: $blue !default;\n$secondary: $gray-600 !default;\n$success: $green !default;\n$info: $cyan !default;\n$warning: $yellow !default;\n$danger: $red !default;\n$light: $gray-100 !default;\n$dark: $gray-800 !default;\n\n$theme-colors: () !default;\n// stylelint-disable-next-line scss/dollar-variable-default\n$theme-colors: map-merge(\n (\n \"primary\": $primary,\n \"secondary\": $secondary,\n \"success\": $success,\n \"info\": $info,\n \"warning\": $warning,\n \"danger\": $danger,\n \"light\": $light,\n \"dark\": $dark\n ),\n $theme-colors\n);\n\n// Set a specific jump point for requesting color jumps\n$theme-color-interval: 8% !default;\n\n// The yiq lightness value that determines when the lightness of color changes from \"dark\" to \"light\". Acceptable values are between 0 and 255.\n$yiq-contrasted-threshold: 150 !default;\n\n// Customize the light and dark text colors for use in our YIQ color contrast function.\n$yiq-text-dark: $gray-900 !default;\n$yiq-text-light: $white !default;\n\n\n// Options\n//\n// Quickly modify global styling by enabling or disabling optional features.\n\n$enable-caret: true !default;\n$enable-rounded: true !default;\n$enable-shadows: false !default;\n$enable-gradients: false !default;\n$enable-transitions: true !default;\n$enable-prefers-reduced-motion-media-query: true !default;\n$enable-hover-media-query: false !default; // Deprecated, no longer affects any compiled CSS\n$enable-grid-classes: true !default;\n$enable-pointer-cursor-for-buttons: true !default;\n$enable-print-styles: true !default;\n$enable-responsive-font-sizes: false !default;\n$enable-validation-icons: true !default;\n$enable-deprecation-messages: true !default;\n\n\n// Spacing\n//\n// Control the default styling of most Bootstrap elements by modifying these\n// variables. Mostly focused on spacing.\n// You can add more entries to the $spacers map, should you need more variation.\n\n$spacer: 1rem !default;\n$spacers: () !default;\n// stylelint-disable-next-line scss/dollar-variable-default\n$spacers: map-merge(\n (\n 0: 0,\n 1: ($spacer * .25),\n 2: ($spacer * .5),\n 3: $spacer,\n 4: ($spacer * 1.5),\n 5: ($spacer * 3)\n ),\n $spacers\n);\n\n// This variable affects the `.h-*` and `.w-*` classes.\n$sizes: () !default;\n// stylelint-disable-next-line scss/dollar-variable-default\n$sizes: map-merge(\n (\n 25: 25%,\n 50: 50%,\n 75: 75%,\n 100: 100%,\n auto: auto\n ),\n $sizes\n);\n\n\n// Body\n//\n// Settings for the `` element.\n\n$body-bg: $white !default;\n$body-color: $gray-900 !default;\n\n\n// Links\n//\n// Style anchor elements.\n\n$link-color: theme-color(\"primary\") !default;\n$link-decoration: none !default;\n$link-hover-color: darken($link-color, 15%) !default;\n$link-hover-decoration: underline !default;\n// Darken percentage for links with `.text-*` class (e.g. `.text-success`)\n$emphasized-link-hover-darken-percentage: 15% !default;\n\n// Paragraphs\n//\n// Style p element.\n\n$paragraph-margin-bottom: 1rem !default;\n\n\n// Grid breakpoints\n//\n// Define the minimum dimensions at which your layout will change,\n// adapting to different screen sizes, for use in media queries.\n\n$grid-breakpoints: (\n xs: 0,\n sm: 576px,\n md: 768px,\n lg: 992px,\n xl: 1200px\n) !default;\n\n@include _assert-ascending($grid-breakpoints, \"$grid-breakpoints\");\n@include _assert-starts-at-zero($grid-breakpoints, \"$grid-breakpoints\");\n\n\n// Grid containers\n//\n// Define the maximum width of `.container` for different screen sizes.\n\n$container-max-widths: (\n sm: 540px,\n md: 720px,\n lg: 960px,\n xl: 1140px\n) !default;\n\n@include _assert-ascending($container-max-widths, \"$container-max-widths\");\n\n\n// Grid columns\n//\n// Set the number of columns and specify the width of the gutters.\n\n$grid-columns: 12 !default;\n$grid-gutter-width: 30px !default;\n\n\n// Components\n//\n// Define common padding and border radius sizes and more.\n\n$line-height-lg: 1.5 !default;\n$line-height-sm: 1.5 !default;\n\n$border-width: 1px !default;\n$border-color: $gray-300 !default;\n\n$border-radius: .25rem !default;\n$border-radius-lg: .3rem !default;\n$border-radius-sm: .2rem !default;\n\n$rounded-pill: 50rem !default;\n\n$box-shadow-sm: 0 .125rem .25rem rgba($black, .075) !default;\n$box-shadow: 0 .5rem 1rem rgba($black, .15) !default;\n$box-shadow-lg: 0 1rem 3rem rgba($black, .175) !default;\n\n$component-active-color: $white !default;\n$component-active-bg: theme-color(\"primary\") !default;\n\n$caret-width: .3em !default;\n$caret-vertical-align: $caret-width * .85 !default;\n$caret-spacing: $caret-width * .85 !default;\n\n$transition-base: all .2s ease-in-out !default;\n$transition-fade: opacity .15s linear !default;\n$transition-collapse: height .35s ease !default;\n\n$embed-responsive-aspect-ratios: () !default;\n// stylelint-disable-next-line scss/dollar-variable-default\n$embed-responsive-aspect-ratios: join(\n (\n (21 9),\n (16 9),\n (4 3),\n (1 1),\n ),\n $embed-responsive-aspect-ratios\n);\n\n// Typography\n//\n// Font, line-height, and color for body text, headings, and more.\n\n// stylelint-disable value-keyword-case\n$font-family-sans-serif: \"Helvetica Neue\", Arial, \"Noto Sans\", -apple-system, BlinkMacSystemFont, \"Segoe UI\", Roboto, sans-serif, \"Apple Color Emoji\", \"Segoe UI Emoji\", \"Segoe UI Symbol\", \"Noto Color Emoji\" !default;\n$font-family-monospace: SFMono-Regular, Menlo, Monaco, Consolas, \"Liberation Mono\", \"Courier New\", monospace !default;\n$font-family-base: $font-family-sans-serif !default;\n// stylelint-enable value-keyword-case\n\n$font-size-base: 1rem !default; // Assumes the browser default, typically `16px`\n$font-size-lg: $font-size-base * 1.25 !default;\n$font-size-sm: $font-size-base * .875 !default;\n\n$font-weight-lighter: lighter !default;\n$font-weight-light: 300 !default;\n$font-weight-normal: 400 !default;\n$font-weight-bold: 700 !default;\n$font-weight-bolder: bolder !default;\n\n$font-weight-base: $font-weight-normal !default;\n$line-height-base: 1.5 !default;\n\n$h1-font-size: $font-size-base * 2.5 !default;\n$h2-font-size: $font-size-base * 2 !default;\n$h3-font-size: $font-size-base * 1.75 !default;\n$h4-font-size: $font-size-base * 1.5 !default;\n$h5-font-size: $font-size-base * 1.25 !default;\n$h6-font-size: $font-size-base !default;\n\n$headings-margin-bottom: $spacer / 2 !default;\n$headings-font-family: null !default;\n$headings-font-weight: 500 !default;\n$headings-line-height: 1.2 !default;\n$headings-color: null !default;\n\n$display1-size: 6rem !default;\n$display2-size: 5.5rem !default;\n$display3-size: 4.5rem !default;\n$display4-size: 3.5rem !default;\n\n$display1-weight: 300 !default;\n$display2-weight: 300 !default;\n$display3-weight: 300 !default;\n$display4-weight: 300 !default;\n$display-line-height: $headings-line-height !default;\n\n$lead-font-size: $font-size-base * 1.25 !default;\n$lead-font-weight: 300 !default;\n\n$small-font-size: 80% !default;\n\n$text-muted: $gray-600 !default;\n\n$blockquote-small-color: $gray-600 !default;\n$blockquote-small-font-size: $small-font-size !default;\n$blockquote-font-size: $font-size-base * 1.25 !default;\n\n$hr-border-color: rgba($black, .1) !default;\n$hr-border-width: $border-width !default;\n\n$mark-padding: .2em !default;\n\n$dt-font-weight: $font-weight-bold !default;\n\n$kbd-box-shadow: inset 0 -.1rem 0 rgba($black, .25) !default;\n$nested-kbd-font-weight: $font-weight-bold !default;\n\n$list-inline-padding: .5rem !default;\n\n$mark-bg: #fcf8e3 !default;\n\n$hr-margin-y: $spacer !default;\n\n\n// Tables\n//\n// Customizes the `.table` component with basic values, each used across all table variations.\n\n$table-cell-padding: .75rem !default;\n$table-cell-padding-sm: .3rem !default;\n\n$table-color: $body-color !default;\n$table-bg: null !default;\n$table-accent-bg: rgba($black, .05) !default;\n$table-hover-color: $table-color !default;\n$table-hover-bg: rgba($black, .075) !default;\n$table-active-bg: $table-hover-bg !default;\n\n$table-border-width: $border-width !default;\n$table-border-color: $border-color !default;\n\n$table-head-bg: $gray-200 !default;\n$table-head-color: $gray-700 !default;\n\n$table-dark-color: $white !default;\n$table-dark-bg: $gray-800 !default;\n$table-dark-accent-bg: rgba($white, .05) !default;\n$table-dark-hover-color: $table-dark-color !default;\n$table-dark-hover-bg: rgba($white, .075) !default;\n$table-dark-border-color: lighten($table-dark-bg, 7.5%) !default;\n$table-dark-color: $white !default;\n\n$table-striped-order: odd !default;\n\n$table-caption-color: $text-muted !default;\n\n$table-bg-level: -9 !default;\n$table-border-level: -6 !default;\n\n\n// Buttons + Forms\n//\n// Shared variables that are reassigned to `$input-` and `$btn-` specific variables.\n\n$input-btn-padding-y: .375rem !default;\n$input-btn-padding-x: .75rem !default;\n$input-btn-font-family: null !default;\n$input-btn-font-size: $font-size-base !default;\n$input-btn-line-height: $line-height-base !default;\n\n$input-btn-focus-width: .2rem !default;\n$input-btn-focus-color: rgba($component-active-bg, .25) !default;\n$input-btn-focus-box-shadow: 0 0 0 $input-btn-focus-width $input-btn-focus-color !default;\n\n$input-btn-padding-y-sm: .25rem !default;\n$input-btn-padding-x-sm: .5rem !default;\n$input-btn-font-size-sm: $font-size-sm !default;\n$input-btn-line-height-sm: $line-height-sm !default;\n\n$input-btn-padding-y-lg: .5rem !default;\n$input-btn-padding-x-lg: 1rem !default;\n$input-btn-font-size-lg: $font-size-lg !default;\n$input-btn-line-height-lg: $line-height-lg !default;\n\n$input-btn-border-width: $border-width !default;\n\n\n// Buttons\n//\n// For each of Bootstrap's buttons, define text, background, and border color.\n\n$btn-padding-y: $input-btn-padding-y !default;\n$btn-padding-x: $input-btn-padding-x !default;\n$btn-font-family: $input-btn-font-family !default;\n$btn-font-size: $input-btn-font-size !default;\n$btn-line-height: $input-btn-line-height !default;\n\n$btn-padding-y-sm: $input-btn-padding-y-sm !default;\n$btn-padding-x-sm: $input-btn-padding-x-sm !default;\n$btn-font-size-sm: $input-btn-font-size-sm !default;\n$btn-line-height-sm: $input-btn-line-height-sm !default;\n\n$btn-padding-y-lg: $input-btn-padding-y-lg !default;\n$btn-padding-x-lg: $input-btn-padding-x-lg !default;\n$btn-font-size-lg: $input-btn-font-size-lg !default;\n$btn-line-height-lg: $input-btn-line-height-lg !default;\n\n$btn-border-width: $input-btn-border-width !default;\n\n$btn-font-weight: $font-weight-normal !default;\n$btn-box-shadow: inset 0 1px 0 rgba($white, .15), 0 1px 1px rgba($black, .075) !default;\n$btn-focus-width: $input-btn-focus-width !default;\n$btn-focus-box-shadow: $input-btn-focus-box-shadow !default;\n$btn-disabled-opacity: .65 !default;\n$btn-active-box-shadow: inset 0 3px 5px rgba($black, .125) !default;\n\n$btn-link-disabled-color: $gray-600 !default;\n\n$btn-block-spacing-y: .5rem !default;\n\n// Allows for customizing button radius independently from global border radius\n$btn-border-radius: $border-radius !default;\n$btn-border-radius-lg: $border-radius-lg !default;\n$btn-border-radius-sm: $border-radius-sm !default;\n\n$btn-transition: color .15s ease-in-out, background-color .15s ease-in-out, border-color .15s ease-in-out, box-shadow .15s ease-in-out !default;\n\n\n// Forms\n\n$label-margin-bottom: .5rem !default;\n\n$input-padding-y: $input-btn-padding-y !default;\n$input-padding-x: $input-btn-padding-x !default;\n$input-font-family: $input-btn-font-family !default;\n$input-font-size: $input-btn-font-size !default;\n$input-font-weight: $font-weight-base !default;\n$input-line-height: $input-btn-line-height !default;\n\n$input-padding-y-sm: $input-btn-padding-y-sm !default;\n$input-padding-x-sm: $input-btn-padding-x-sm !default;\n$input-font-size-sm: $input-btn-font-size-sm !default;\n$input-line-height-sm: $input-btn-line-height-sm !default;\n\n$input-padding-y-lg: $input-btn-padding-y-lg !default;\n$input-padding-x-lg: $input-btn-padding-x-lg !default;\n$input-font-size-lg: $input-btn-font-size-lg !default;\n$input-line-height-lg: $input-btn-line-height-lg !default;\n\n$input-bg: $white !default;\n$input-disabled-bg: $gray-200 !default;\n\n$input-color: $gray-700 !default;\n$input-border-color: $gray-400 !default;\n$input-border-width: $input-btn-border-width !default;\n$input-box-shadow: inset 0 1px 1px rgba($black, .075) !default;\n\n$input-border-radius: $border-radius !default;\n$input-border-radius-lg: $border-radius-lg !default;\n$input-border-radius-sm: $border-radius-sm !default;\n\n$input-focus-bg: $input-bg !default;\n$input-focus-border-color: lighten($component-active-bg, 25%) !default;\n$input-focus-color: $input-color !default;\n$input-focus-width: $input-btn-focus-width !default;\n$input-focus-box-shadow: $input-btn-focus-box-shadow !default;\n\n$input-placeholder-color: $gray-600 !default;\n$input-plaintext-color: $body-color !default;\n\n$input-height-border: $input-border-width * 2 !default;\n\n$input-height-inner: calc(#{$input-line-height * 1em} + #{$input-padding-y * 2}) !default;\n$input-height-inner-half: calc(#{$input-line-height * .5em} + #{$input-padding-y}) !default;\n$input-height-inner-quarter: calc(#{$input-line-height * .25em} + #{$input-padding-y / 2}) !default;\n\n$input-height: calc(#{$input-line-height * 1em} + #{$input-padding-y * 2} + #{$input-height-border}) !default;\n$input-height-sm: calc(#{$input-line-height-sm * 1em} + #{$input-btn-padding-y-sm * 2} + #{$input-height-border}) !default;\n$input-height-lg: calc(#{$input-line-height-lg * 1em} + #{$input-btn-padding-y-lg * 2} + #{$input-height-border}) !default;\n\n$input-transition: border-color .15s ease-in-out, box-shadow .15s ease-in-out !default;\n\n$form-text-margin-top: .25rem !default;\n\n$form-check-input-gutter: 1.25rem !default;\n$form-check-input-margin-y: .3rem !default;\n$form-check-input-margin-x: .25rem !default;\n\n$form-check-inline-margin-x: .75rem !default;\n$form-check-inline-input-margin-x: .3125rem !default;\n\n$form-grid-gutter-width: 10px !default;\n$form-group-margin-bottom: 1rem !default;\n\n$input-group-addon-color: $input-color !default;\n$input-group-addon-bg: $gray-200 !default;\n$input-group-addon-border-color: $input-border-color !default;\n\n$custom-forms-transition: background-color .15s ease-in-out, border-color .15s ease-in-out, box-shadow .15s ease-in-out !default;\n\n$custom-control-gutter: .5rem !default;\n$custom-control-spacer-x: 1rem !default;\n\n$custom-control-indicator-size: 1rem !default;\n$custom-control-indicator-bg: $input-bg !default;\n\n$custom-control-indicator-bg-size: 50% 50% !default;\n$custom-control-indicator-box-shadow: $input-box-shadow !default;\n$custom-control-indicator-border-color: $gray-500 !default;\n$custom-control-indicator-border-width: $input-border-width !default;\n\n$custom-control-indicator-disabled-bg: $input-disabled-bg !default;\n$custom-control-label-disabled-color: $gray-600 !default;\n\n$custom-control-indicator-checked-color: $component-active-color !default;\n$custom-control-indicator-checked-bg: $component-active-bg !default;\n$custom-control-indicator-checked-disabled-bg: rgba(theme-color(\"primary\"), .5) !default;\n$custom-control-indicator-checked-box-shadow: none !default;\n$custom-control-indicator-checked-border-color: $custom-control-indicator-checked-bg !default;\n\n$custom-control-indicator-focus-box-shadow: $input-focus-box-shadow !default;\n$custom-control-indicator-focus-border-color: $input-focus-border-color !default;\n\n$custom-control-indicator-active-color: $component-active-color !default;\n$custom-control-indicator-active-bg: lighten($component-active-bg, 35%) !default;\n$custom-control-indicator-active-box-shadow: none !default;\n$custom-control-indicator-active-border-color: $custom-control-indicator-active-bg !default;\n\n$custom-checkbox-indicator-border-radius: $border-radius !default;\n$custom-checkbox-indicator-icon-checked: str-replace(url(\"data:image/svg+xml,%3csvg xmlns='http://www.w3.org/2000/svg' viewBox='0 0 8 8'%3e%3cpath fill='#{$custom-control-indicator-checked-color}' d='M6.564.75l-3.59 3.612-1.538-1.55L0 4.26 2.974 7.25 8 2.193z'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n\n$custom-checkbox-indicator-indeterminate-bg: $component-active-bg !default;\n$custom-checkbox-indicator-indeterminate-color: $custom-control-indicator-checked-color !default;\n$custom-checkbox-indicator-icon-indeterminate: str-replace(url(\"data:image/svg+xml,%3csvg xmlns='http://www.w3.org/2000/svg' viewBox='0 0 4 4'%3e%3cpath stroke='#{$custom-checkbox-indicator-indeterminate-color}' d='M0 2h4'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n$custom-checkbox-indicator-indeterminate-box-shadow: none !default;\n$custom-checkbox-indicator-indeterminate-border-color: $custom-checkbox-indicator-indeterminate-bg !default;\n\n$custom-radio-indicator-border-radius: 50% !default;\n$custom-radio-indicator-icon-checked: str-replace(url(\"data:image/svg+xml,%3csvg xmlns='http://www.w3.org/2000/svg' viewBox='-4 -4 8 8'%3e%3ccircle r='3' fill='#{$custom-control-indicator-checked-color}'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n\n$custom-switch-width: $custom-control-indicator-size * 1.75 !default;\n$custom-switch-indicator-border-radius: $custom-control-indicator-size / 2 !default;\n$custom-switch-indicator-size: calc(#{$custom-control-indicator-size} - #{$custom-control-indicator-border-width * 4}) !default;\n\n$custom-select-padding-y: $input-padding-y !default;\n$custom-select-padding-x: $input-padding-x !default;\n$custom-select-font-family: $input-font-family !default;\n$custom-select-font-size: $input-font-size !default;\n$custom-select-height: $input-height !default;\n$custom-select-indicator-padding: 1rem !default; // Extra padding to account for the presence of the background-image based indicator\n$custom-select-font-weight: $input-font-weight !default;\n$custom-select-line-height: $input-line-height !default;\n$custom-select-color: $input-color !default;\n$custom-select-disabled-color: $gray-600 !default;\n$custom-select-bg: $input-bg !default;\n$custom-select-disabled-bg: $gray-200 !default;\n$custom-select-bg-size: 8px 10px !default; // In pixels because image dimensions\n$custom-select-indicator-color: $gray-800 !default;\n$custom-select-indicator: str-replace(url(\"data:image/svg+xml,%3csvg xmlns='http://www.w3.org/2000/svg' viewBox='0 0 4 5'%3e%3cpath fill='#{$custom-select-indicator-color}' d='M2 0L0 2h4zm0 5L0 3h4z'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n$custom-select-background: $custom-select-indicator no-repeat right $custom-select-padding-x center / $custom-select-bg-size !default; // Used so we can have multiple background elements (e.g., arrow and feedback icon)\n\n$custom-select-feedback-icon-padding-right: calc((1em + #{2 * $custom-select-padding-y}) * 3 / 4 + #{$custom-select-padding-x + $custom-select-indicator-padding}) !default;\n$custom-select-feedback-icon-position: center right ($custom-select-padding-x + $custom-select-indicator-padding) !default;\n$custom-select-feedback-icon-size: $input-height-inner-half $input-height-inner-half !default;\n\n$custom-select-border-width: $input-border-width !default;\n$custom-select-border-color: $input-border-color !default;\n$custom-select-border-radius: $border-radius !default;\n$custom-select-box-shadow: inset 0 1px 2px rgba($black, .075) !default;\n\n$custom-select-focus-border-color: $input-focus-border-color !default;\n$custom-select-focus-width: $input-focus-width !default;\n$custom-select-focus-box-shadow: 0 0 0 $custom-select-focus-width $input-btn-focus-color !default;\n\n$custom-select-padding-y-sm: $input-padding-y-sm !default;\n$custom-select-padding-x-sm: $input-padding-x-sm !default;\n$custom-select-font-size-sm: $input-font-size-sm !default;\n$custom-select-height-sm: $input-height-sm !default;\n\n$custom-select-padding-y-lg: $input-padding-y-lg !default;\n$custom-select-padding-x-lg: $input-padding-x-lg !default;\n$custom-select-font-size-lg: $input-font-size-lg !default;\n$custom-select-height-lg: $input-height-lg !default;\n\n$custom-range-track-width: 100% !default;\n$custom-range-track-height: .5rem !default;\n$custom-range-track-cursor: pointer !default;\n$custom-range-track-bg: $gray-300 !default;\n$custom-range-track-border-radius: 1rem !default;\n$custom-range-track-box-shadow: inset 0 .25rem .25rem rgba($black, .1) !default;\n\n$custom-range-thumb-width: 1rem !default;\n$custom-range-thumb-height: $custom-range-thumb-width !default;\n$custom-range-thumb-bg: $component-active-bg !default;\n$custom-range-thumb-border: 0 !default;\n$custom-range-thumb-border-radius: 1rem !default;\n$custom-range-thumb-box-shadow: 0 .1rem .25rem rgba($black, .1) !default;\n$custom-range-thumb-focus-box-shadow: 0 0 0 1px $body-bg, $input-focus-box-shadow !default;\n$custom-range-thumb-focus-box-shadow-width: $input-focus-width !default; // For focus box shadow issue in IE/Edge\n$custom-range-thumb-active-bg: lighten($component-active-bg, 35%) !default;\n$custom-range-thumb-disabled-bg: $gray-500 !default;\n\n$custom-file-height: $input-height !default;\n$custom-file-height-inner: $input-height-inner !default;\n$custom-file-focus-border-color: $input-focus-border-color !default;\n$custom-file-focus-box-shadow: $input-focus-box-shadow !default;\n$custom-file-disabled-bg: $input-disabled-bg !default;\n\n$custom-file-padding-y: $input-padding-y !default;\n$custom-file-padding-x: $input-padding-x !default;\n$custom-file-line-height: $input-line-height !default;\n$custom-file-font-family: $input-font-family !default;\n$custom-file-font-weight: $input-font-weight !default;\n$custom-file-color: $input-color !default;\n$custom-file-bg: $input-bg !default;\n$custom-file-border-width: $input-border-width !default;\n$custom-file-border-color: $input-border-color !default;\n$custom-file-border-radius: $input-border-radius !default;\n$custom-file-box-shadow: $input-box-shadow !default;\n$custom-file-button-color: $custom-file-color !default;\n$custom-file-button-bg: $input-group-addon-bg !default;\n$custom-file-text: (\n en: \"Browse\"\n) !default;\n\n\n// Form validation\n\n$form-feedback-margin-top: $form-text-margin-top !default;\n$form-feedback-font-size: $small-font-size !default;\n$form-feedback-valid-color: theme-color(\"success\") !default;\n$form-feedback-invalid-color: theme-color(\"danger\") !default;\n\n$form-feedback-icon-valid-color: $form-feedback-valid-color !default;\n$form-feedback-icon-valid: str-replace(url(\"data:image/svg+xml,%3csvg xmlns='http://www.w3.org/2000/svg' viewBox='0 0 8 8'%3e%3cpath fill='#{$form-feedback-icon-valid-color}' d='M2.3 6.73L.6 4.53c-.4-1.04.46-1.4 1.1-.8l1.1 1.4 3.4-3.8c.6-.63 1.6-.27 1.2.7l-4 4.6c-.43.5-.8.4-1.1.1z'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n$form-feedback-icon-invalid-color: $form-feedback-invalid-color !default;\n$form-feedback-icon-invalid: str-replace(url(\"data:image/svg+xml,%3csvg xmlns='http://www.w3.org/2000/svg' fill='#{$form-feedback-icon-invalid-color}' viewBox='-2 -2 7 7'%3e%3cpath stroke='#{$form-feedback-icon-invalid-color}' d='M0 0l3 3m0-3L0 3'/%3e%3ccircle r='.5'/%3e%3ccircle cx='3' r='.5'/%3e%3ccircle cy='3' r='.5'/%3e%3ccircle cx='3' cy='3' r='.5'/%3e%3c/svg%3E\"), \"#\", \"%23\") !default;\n\n$form-validation-states: () !default;\n// stylelint-disable-next-line scss/dollar-variable-default\n$form-validation-states: map-merge(\n (\n \"valid\": (\n \"color\": $form-feedback-valid-color,\n \"icon\": $form-feedback-icon-valid\n ),\n \"invalid\": (\n \"color\": $form-feedback-invalid-color,\n \"icon\": $form-feedback-icon-invalid\n ),\n ),\n $form-validation-states\n);\n\n// Z-index master list\n//\n// Warning: Avoid customizing these values. They're used for a bird's eye view\n// of components dependent on the z-axis and are designed to all work together.\n\n$zindex-dropdown: 1000 !default;\n$zindex-sticky: 1020 !default;\n$zindex-fixed: 1030 !default;\n$zindex-modal-backdrop: 1040 !default;\n$zindex-modal: 1050 !default;\n$zindex-popover: 1060 !default;\n$zindex-tooltip: 1070 !default;\n\n\n// Navs\n\n$nav-link-padding-y: .5rem !default;\n$nav-link-padding-x: 1rem !default;\n$nav-link-disabled-color: $gray-600 !default;\n\n$nav-tabs-border-color: $gray-300 !default;\n$nav-tabs-border-width: $border-width !default;\n$nav-tabs-border-radius: $border-radius !default;\n$nav-tabs-link-hover-border-color: $gray-200 $gray-200 $nav-tabs-border-color !default;\n$nav-tabs-link-active-color: $gray-700 !default;\n$nav-tabs-link-active-bg: $body-bg !default;\n$nav-tabs-link-active-border-color: $gray-300 $gray-300 $nav-tabs-link-active-bg !default;\n\n$nav-pills-border-radius: $border-radius !default;\n$nav-pills-link-active-color: $component-active-color !default;\n$nav-pills-link-active-bg: $component-active-bg !default;\n\n$nav-divider-color: $gray-200 !default;\n$nav-divider-margin-y: $spacer / 2 !default;\n\n\n// Navbar\n\n$navbar-padding-y: $spacer / 2 !default;\n$navbar-padding-x: $spacer !default;\n\n$navbar-nav-link-padding-x: .5rem !default;\n\n$navbar-brand-font-size: $font-size-lg !default;\n// Compute the navbar-brand padding-y so the navbar-brand will have the same height as navbar-text and nav-link\n$nav-link-height: $font-size-base * $line-height-base + $nav-link-padding-y * 2 !default;\n$navbar-brand-height: $navbar-brand-font-size * $line-height-base !default;\n$navbar-brand-padding-y: ($nav-link-height - $navbar-brand-height) / 2 !default;\n\n$navbar-toggler-padding-y: .25rem !default;\n$navbar-toggler-padding-x: .75rem !default;\n$navbar-toggler-font-size: $font-size-lg !default;\n$navbar-toggler-border-radius: $btn-border-radius !default;\n\n$navbar-dark-color: rgba($white, .5) !default;\n$navbar-dark-hover-color: rgba($white, .75) !default;\n$navbar-dark-active-color: $white !default;\n$navbar-dark-disabled-color: rgba($white, .25) !default;\n$navbar-dark-toggler-icon-bg: str-replace(url(\"data:image/svg+xml,%3csvg viewBox='0 0 30 30' xmlns='http://www.w3.org/2000/svg'%3e%3cpath stroke='#{$navbar-dark-color}' stroke-width='2' stroke-linecap='round' stroke-miterlimit='10' d='M4 7h22M4 15h22M4 23h22'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n$navbar-dark-toggler-border-color: rgba($white, .1) !default;\n\n$navbar-light-color: rgba($black, .5) !default;\n$navbar-light-hover-color: rgba($black, .7) !default;\n$navbar-light-active-color: rgba($black, .9) !default;\n$navbar-light-disabled-color: rgba($black, .3) !default;\n$navbar-light-toggler-icon-bg: str-replace(url(\"data:image/svg+xml,%3csvg viewBox='0 0 30 30' xmlns='http://www.w3.org/2000/svg'%3e%3cpath stroke='#{$navbar-light-color}' stroke-width='2' stroke-linecap='round' stroke-miterlimit='10' d='M4 7h22M4 15h22M4 23h22'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n$navbar-light-toggler-border-color: rgba($black, .1) !default;\n\n$navbar-light-brand-color: $navbar-light-active-color !default;\n$navbar-light-brand-hover-color: $navbar-light-active-color !default;\n$navbar-dark-brand-color: $navbar-dark-active-color !default;\n$navbar-dark-brand-hover-color: $navbar-dark-active-color !default;\n\n\n// Dropdowns\n//\n// Dropdown menu container and contents.\n\n$dropdown-min-width: 10rem !default;\n$dropdown-padding-y: .5rem !default;\n$dropdown-spacer: .125rem !default;\n$dropdown-font-size: $font-size-base !default;\n$dropdown-color: $body-color !default;\n$dropdown-bg: $white !default;\n$dropdown-border-color: rgba($black, .15) !default;\n$dropdown-border-radius: $border-radius !default;\n$dropdown-border-width: $border-width !default;\n$dropdown-inner-border-radius: calc(#{$dropdown-border-radius} - #{$dropdown-border-width}) !default;\n$dropdown-divider-bg: $gray-200 !default;\n$dropdown-divider-margin-y: $nav-divider-margin-y !default;\n$dropdown-box-shadow: 0 .5rem 1rem rgba($black, .175) !default;\n\n$dropdown-link-color: $gray-900 !default;\n$dropdown-link-hover-color: darken($gray-900, 5%) !default;\n$dropdown-link-hover-bg: $gray-100 !default;\n\n$dropdown-link-active-color: $component-active-color !default;\n$dropdown-link-active-bg: $component-active-bg !default;\n\n$dropdown-link-disabled-color: $gray-600 !default;\n\n$dropdown-item-padding-y: .25rem !default;\n$dropdown-item-padding-x: 1.5rem !default;\n\n$dropdown-header-color: $gray-600 !default;\n\n\n// Pagination\n\n$pagination-padding-y: .5rem !default;\n$pagination-padding-x: .75rem !default;\n$pagination-padding-y-sm: .25rem !default;\n$pagination-padding-x-sm: .5rem !default;\n$pagination-padding-y-lg: .75rem !default;\n$pagination-padding-x-lg: 1.5rem !default;\n$pagination-line-height: 1.25 !default;\n\n$pagination-color: $link-color !default;\n$pagination-bg: $white !default;\n$pagination-border-width: $border-width !default;\n$pagination-border-color: $gray-300 !default;\n\n$pagination-focus-box-shadow: $input-btn-focus-box-shadow !default;\n$pagination-focus-outline: 0 !default;\n\n$pagination-hover-color: $link-hover-color !default;\n$pagination-hover-bg: $gray-200 !default;\n$pagination-hover-border-color: $gray-300 !default;\n\n$pagination-active-color: $component-active-color !default;\n$pagination-active-bg: $component-active-bg !default;\n$pagination-active-border-color: $pagination-active-bg !default;\n\n$pagination-disabled-color: $gray-600 !default;\n$pagination-disabled-bg: $white !default;\n$pagination-disabled-border-color: $gray-300 !default;\n\n\n// Jumbotron\n\n$jumbotron-padding: 2rem !default;\n$jumbotron-color: null !default;\n$jumbotron-bg: $gray-200 !default;\n\n\n// Cards\n\n$card-spacer-y: .75rem !default;\n$card-spacer-x: 1.25rem !default;\n$card-border-width: $border-width !default;\n$card-border-radius: $border-radius !default;\n$card-border-color: rgba($black, .125) !default;\n$card-inner-border-radius: calc(#{$card-border-radius} - #{$card-border-width}) !default;\n$card-cap-bg: rgba($black, .03) !default;\n$card-cap-color: null !default;\n$card-color: null !default;\n$card-bg: $white !default;\n\n$card-img-overlay-padding: 1.25rem !default;\n\n$card-group-margin: $grid-gutter-width / 2 !default;\n$card-deck-margin: $card-group-margin !default;\n\n$card-columns-count: 3 !default;\n$card-columns-gap: 1.25rem !default;\n$card-columns-margin: $card-spacer-y !default;\n\n\n// Tooltips\n\n$tooltip-font-size: $font-size-sm !default;\n$tooltip-max-width: 200px !default;\n$tooltip-color: $white !default;\n$tooltip-bg: $black !default;\n$tooltip-border-radius: $border-radius !default;\n$tooltip-opacity: .9 !default;\n$tooltip-padding-y: .25rem !default;\n$tooltip-padding-x: .5rem !default;\n$tooltip-margin: 0 !default;\n\n$tooltip-arrow-width: .8rem !default;\n$tooltip-arrow-height: .4rem !default;\n$tooltip-arrow-color: $tooltip-bg !default;\n\n// Form tooltips must come after regular tooltips\n$form-feedback-tooltip-padding-y: $tooltip-padding-y !default;\n$form-feedback-tooltip-padding-x: $tooltip-padding-x !default;\n$form-feedback-tooltip-font-size: $tooltip-font-size !default;\n$form-feedback-tooltip-line-height: $line-height-base !default;\n$form-feedback-tooltip-opacity: $tooltip-opacity !default;\n$form-feedback-tooltip-border-radius: $tooltip-border-radius !default;\n\n\n// Popovers\n\n$popover-font-size: $font-size-sm !default;\n$popover-bg: $white !default;\n$popover-max-width: 276px !default;\n$popover-border-width: $border-width !default;\n$popover-border-color: rgba($black, .2) !default;\n$popover-border-radius: $border-radius-lg !default;\n$popover-box-shadow: 0 .25rem .5rem rgba($black, .2) !default;\n\n$popover-header-bg: darken($popover-bg, 3%) !default;\n$popover-header-color: $headings-color !default;\n$popover-header-padding-y: .5rem !default;\n$popover-header-padding-x: .75rem !default;\n\n$popover-body-color: $body-color !default;\n$popover-body-padding-y: $popover-header-padding-y !default;\n$popover-body-padding-x: $popover-header-padding-x !default;\n\n$popover-arrow-width: 1rem !default;\n$popover-arrow-height: .5rem !default;\n$popover-arrow-color: $popover-bg !default;\n\n$popover-arrow-outer-color: fade-in($popover-border-color, .05) !default;\n\n\n// Toasts\n\n$toast-max-width: 350px !default;\n$toast-padding-x: .75rem !default;\n$toast-padding-y: .25rem !default;\n$toast-font-size: .875rem !default;\n$toast-color: null !default;\n$toast-background-color: rgba($white, .85) !default;\n$toast-border-width: 1px !default;\n$toast-border-color: rgba(0, 0, 0, .1) !default;\n$toast-border-radius: .25rem !default;\n$toast-box-shadow: 0 .25rem .75rem rgba($black, .1) !default;\n\n$toast-header-color: $gray-600 !default;\n$toast-header-background-color: rgba($white, .85) !default;\n$toast-header-border-color: rgba(0, 0, 0, .05) !default;\n\n\n// Badges\n\n$badge-font-size: 75% !default;\n$badge-font-weight: $font-weight-bold !default;\n$badge-padding-y: .25em !default;\n$badge-padding-x: .4em !default;\n$badge-border-radius: $border-radius !default;\n\n$badge-transition: $btn-transition !default;\n$badge-focus-width: $input-btn-focus-width !default;\n\n$badge-pill-padding-x: .6em !default;\n// Use a higher than normal value to ensure completely rounded edges when\n// customizing padding or font-size on labels.\n$badge-pill-border-radius: 10rem !default;\n\n\n// Modals\n\n// Padding applied to the modal body\n$modal-inner-padding: 1rem !default;\n\n$modal-dialog-margin: .5rem !default;\n$modal-dialog-margin-y-sm-up: 1.75rem !default;\n\n$modal-title-line-height: $line-height-base !default;\n\n$modal-content-color: null !default;\n$modal-content-bg: $white !default;\n$modal-content-border-color: rgba($black, .2) !default;\n$modal-content-border-width: $border-width !default;\n$modal-content-border-radius: $border-radius-lg !default;\n$modal-content-box-shadow-xs: 0 .25rem .5rem rgba($black, .5) !default;\n$modal-content-box-shadow-sm-up: 0 .5rem 1rem rgba($black, .5) !default;\n\n$modal-backdrop-bg: $black !default;\n$modal-backdrop-opacity: .5 !default;\n$modal-header-border-color: $border-color !default;\n$modal-footer-border-color: $modal-header-border-color !default;\n$modal-header-border-width: $modal-content-border-width !default;\n$modal-footer-border-width: $modal-header-border-width !default;\n$modal-header-padding-y: 1rem !default;\n$modal-header-padding-x: 1rem !default;\n$modal-header-padding: $modal-header-padding-y $modal-header-padding-x !default; // Keep this for backwards compatibility\n\n$modal-xl: 1140px !default;\n$modal-lg: 800px !default;\n$modal-md: 500px !default;\n$modal-sm: 300px !default;\n\n$modal-fade-transform: translate(0, -50px) !default;\n$modal-show-transform: none !default;\n$modal-transition: transform .3s ease-out !default;\n\n\n// Alerts\n//\n// Define alert colors, border radius, and padding.\n\n$alert-padding-y: .75rem !default;\n$alert-padding-x: 1.25rem !default;\n$alert-margin-bottom: 1rem !default;\n$alert-border-radius: $border-radius !default;\n$alert-link-font-weight: $font-weight-bold !default;\n$alert-border-width: $border-width !default;\n\n$alert-bg-level: -10 !default;\n$alert-border-level: -9 !default;\n$alert-color-level: 6 !default;\n\n\n// Progress bars\n\n$progress-height: 1rem !default;\n$progress-font-size: $font-size-base * .75 !default;\n$progress-bg: $gray-200 !default;\n$progress-border-radius: $border-radius !default;\n$progress-box-shadow: inset 0 .1rem .1rem rgba($black, .1) !default;\n$progress-bar-color: $white !default;\n$progress-bar-bg: theme-color(\"primary\") !default;\n$progress-bar-animation-timing: 1s linear infinite !default;\n$progress-bar-transition: width .6s ease !default;\n\n\n// List group\n\n$list-group-color: null !default;\n$list-group-bg: $white !default;\n$list-group-border-color: rgba($black, .125) !default;\n$list-group-border-width: $border-width !default;\n$list-group-border-radius: $border-radius !default;\n\n$list-group-item-padding-y: .75rem !default;\n$list-group-item-padding-x: 1.25rem !default;\n\n$list-group-hover-bg: $gray-100 !default;\n$list-group-active-color: $component-active-color !default;\n$list-group-active-bg: $component-active-bg !default;\n$list-group-active-border-color: $list-group-active-bg !default;\n\n$list-group-disabled-color: $gray-600 !default;\n$list-group-disabled-bg: $list-group-bg !default;\n\n$list-group-action-color: $gray-700 !default;\n$list-group-action-hover-color: $list-group-action-color !default;\n\n$list-group-action-active-color: $body-color !default;\n$list-group-action-active-bg: $gray-200 !default;\n\n\n// Image thumbnails\n\n$thumbnail-padding: .25rem !default;\n$thumbnail-bg: $body-bg !default;\n$thumbnail-border-width: $border-width !default;\n$thumbnail-border-color: $gray-300 !default;\n$thumbnail-border-radius: $border-radius !default;\n$thumbnail-box-shadow: 0 1px 2px rgba($black, .075) !default;\n\n\n// Figures\n\n$figure-caption-font-size: 90% !default;\n$figure-caption-color: $gray-600 !default;\n\n\n// Breadcrumbs\n\n$breadcrumb-padding-y: .75rem !default;\n$breadcrumb-padding-x: 1rem !default;\n$breadcrumb-item-padding: .5rem !default;\n\n$breadcrumb-margin-bottom: 1rem !default;\n\n$breadcrumb-bg: $gray-200 !default;\n$breadcrumb-divider-color: $gray-600 !default;\n$breadcrumb-active-color: $gray-600 !default;\n$breadcrumb-divider: quote(\"/\") !default;\n\n$breadcrumb-border-radius: $border-radius !default;\n\n\n// Carousel\n\n$carousel-control-color: $white !default;\n$carousel-control-width: 15% !default;\n$carousel-control-opacity: .5 !default;\n$carousel-control-hover-opacity: .9 !default;\n$carousel-control-transition: opacity .15s ease !default;\n\n$carousel-indicator-width: 30px !default;\n$carousel-indicator-height: 3px !default;\n$carousel-indicator-hit-area-height: 10px !default;\n$carousel-indicator-spacer: 3px !default;\n$carousel-indicator-active-bg: $white !default;\n$carousel-indicator-transition: opacity .6s ease !default;\n\n$carousel-caption-width: 70% !default;\n$carousel-caption-color: $white !default;\n\n$carousel-control-icon-width: 20px !default;\n\n$carousel-control-prev-icon-bg: str-replace(url(\"data:image/svg+xml,%3csvg xmlns='http://www.w3.org/2000/svg' fill='#{$carousel-control-color}' viewBox='0 0 8 8'%3e%3cpath d='M5.25 0l-4 4 4 4 1.5-1.5-2.5-2.5 2.5-2.5-1.5-1.5z'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n$carousel-control-next-icon-bg: str-replace(url(\"data:image/svg+xml,%3csvg xmlns='http://www.w3.org/2000/svg' fill='#{$carousel-control-color}' viewBox='0 0 8 8'%3e%3cpath d='M2.75 0l-1.5 1.5 2.5 2.5-2.5 2.5 1.5 1.5 4-4-4-4z'/%3e%3c/svg%3e\"), \"#\", \"%23\") !default;\n\n$carousel-transition-duration: .6s !default;\n$carousel-transition: transform $carousel-transition-duration ease-in-out !default; // Define transform transition first if using multiple transitions (e.g., `transform 2s ease, opacity .5s ease-out`)\n\n\n// Spinners\n\n$spinner-width: 2rem !default;\n$spinner-height: $spinner-width !default;\n$spinner-border-width: .25em !default;\n\n$spinner-width-sm: 1rem !default;\n$spinner-height-sm: $spinner-width-sm !default;\n$spinner-border-width-sm: .2em !default;\n\n\n// Close\n\n$close-font-size: $font-size-base * 1.5 !default;\n$close-font-weight: $font-weight-bold !default;\n$close-color: $black !default;\n$close-text-shadow: 0 1px 0 $white !default;\n\n\n// Code\n\n$code-font-size: 87.5% !default;\n$code-color: $pink !default;\n\n$kbd-padding-y: .2rem !default;\n$kbd-padding-x: .4rem !default;\n$kbd-font-size: $code-font-size !default;\n$kbd-color: $white !default;\n$kbd-bg: $gray-900 !default;\n\n$pre-color: $gray-900 !default;\n$pre-scrollable-max-height: 340px !default;\n\n\n// Utilities\n\n$displays: none, inline, inline-block, block, table, table-row, table-cell, flex, inline-flex !default;\n$overflows: auto, hidden !default;\n$positions: static, relative, absolute, fixed, sticky !default;\n\n\n// Printing\n\n$print-page-size: a3 !default;\n$print-body-min-width: map-get($grid-breakpoints, \"lg\") !default;\n", + "// Toggles\n//\n// Used in conjunction with global variables to enable certain theme features.\n\n// Vendor\n@import \"vendor/rfs\";\n\n// Deprecate\n@import \"mixins/deprecate\";\n\n// Utilities\n@import \"mixins/breakpoints\";\n@import \"mixins/hover\";\n@import \"mixins/image\";\n@import \"mixins/badge\";\n@import \"mixins/resize\";\n@import \"mixins/screen-reader\";\n@import \"mixins/size\";\n@import \"mixins/reset-text\";\n@import \"mixins/text-emphasis\";\n@import \"mixins/text-hide\";\n@import \"mixins/text-truncate\";\n@import \"mixins/visibility\";\n\n// // Components\n@import \"mixins/alert\";\n@import \"mixins/buttons\";\n@import \"mixins/caret\";\n@import \"mixins/pagination\";\n@import \"mixins/lists\";\n@import \"mixins/list-group\";\n@import \"mixins/nav-divider\";\n@import \"mixins/forms\";\n@import \"mixins/table-row\";\n\n// // Skins\n@import \"mixins/background-variant\";\n@import \"mixins/border-radius\";\n@import \"mixins/box-shadow\";\n@import \"mixins/gradients\";\n@import \"mixins/transition\";\n\n// // Layout\n@import \"mixins/clearfix\";\n@import \"mixins/grid-framework\";\n@import \"mixins/grid\";\n@import \"mixins/float\";\n", + "// stylelint-disable property-blacklist, scss/dollar-variable-default\n\n// SCSS RFS mixin\n//\n// Automated font-resizing\n//\n// See https://github.com/twbs/rfs\n\n// Configuration\n\n// Base font size\n$rfs-base-font-size: 1.25rem !default;\n$rfs-font-size-unit: rem !default;\n\n// Breakpoint at where font-size starts decreasing if screen width is smaller\n$rfs-breakpoint: 1200px !default;\n$rfs-breakpoint-unit: px !default;\n\n// Resize font-size based on screen height and width\n$rfs-two-dimensional: false !default;\n\n// Factor of decrease\n$rfs-factor: 10 !default;\n\n@if type-of($rfs-factor) != \"number\" or $rfs-factor <= 1 {\n @error \"`#{$rfs-factor}` is not a valid $rfs-factor, it must be greater than 1.\";\n}\n\n// Generate enable or disable classes. Possibilities: false, \"enable\" or \"disable\"\n$rfs-class: false !default;\n\n// 1 rem = $rfs-rem-value px\n$rfs-rem-value: 16 !default;\n\n// Safari iframe resize bug: https://github.com/twbs/rfs/issues/14\n$rfs-safari-iframe-resize-bug-fix: false !default;\n\n// Disable RFS by setting $enable-responsive-font-sizes to false\n$enable-responsive-font-sizes: true !default;\n\n// Cache $rfs-base-font-size unit\n$rfs-base-font-size-unit: unit($rfs-base-font-size);\n\n// Remove px-unit from $rfs-base-font-size for calculations\n@if $rfs-base-font-size-unit == \"px\" {\n $rfs-base-font-size: $rfs-base-font-size / ($rfs-base-font-size * 0 + 1);\n}\n@else if $rfs-base-font-size-unit == \"rem\" {\n $rfs-base-font-size: $rfs-base-font-size / ($rfs-base-font-size * 0 + 1 / $rfs-rem-value);\n}\n\n// Cache $rfs-breakpoint unit to prevent multiple calls\n$rfs-breakpoint-unit-cache: unit($rfs-breakpoint);\n\n// Remove unit from $rfs-breakpoint for calculations\n@if $rfs-breakpoint-unit-cache == \"px\" {\n $rfs-breakpoint: $rfs-breakpoint / ($rfs-breakpoint * 0 + 1);\n}\n@else if $rfs-breakpoint-unit-cache == \"rem\" or $rfs-breakpoint-unit-cache == \"em\" {\n $rfs-breakpoint: $rfs-breakpoint / ($rfs-breakpoint * 0 + 1 / $rfs-rem-value);\n}\n\n// Responsive font-size mixin\n@mixin rfs($fs, $important: false) {\n // Cache $fs unit\n $fs-unit: if(type-of($fs) == \"number\", unit($fs), false);\n\n // Add !important suffix if needed\n $rfs-suffix: if($important, \" !important\", \"\");\n\n // If $fs isn't a number (like inherit) or $fs has a unit (not px or rem, like 1.5em) or $ is 0, just print the value\n @if not $fs-unit or $fs-unit != \"\" and $fs-unit != \"px\" and $fs-unit != \"rem\" or $fs == 0 {\n font-size: #{$fs}#{$rfs-suffix};\n }\n @else {\n // Variables for storing static and fluid rescaling\n $rfs-static: null;\n $rfs-fluid: null;\n\n // Remove px-unit from $fs for calculations\n @if $fs-unit == \"px\" {\n $fs: $fs / ($fs * 0 + 1);\n }\n @else if $fs-unit == \"rem\" {\n $fs: $fs / ($fs * 0 + 1 / $rfs-rem-value);\n }\n\n // Set default font-size\n @if $rfs-font-size-unit == rem {\n $rfs-static: #{$fs / $rfs-rem-value}rem#{$rfs-suffix};\n }\n @else if $rfs-font-size-unit == px {\n $rfs-static: #{$fs}px#{$rfs-suffix};\n }\n @else {\n @error \"`#{$rfs-font-size-unit}` is not a valid unit for $rfs-font-size-unit. Use `px` or `rem`.\";\n }\n\n // Only add media query if font-size is bigger as the minimum font-size\n // If $rfs-factor == 1, no rescaling will take place\n @if $fs > $rfs-base-font-size and $enable-responsive-font-sizes {\n $min-width: null;\n $variable-unit: null;\n\n // Calculate minimum font-size for given font-size\n $fs-min: $rfs-base-font-size + ($fs - $rfs-base-font-size) / $rfs-factor;\n\n // Calculate difference between given font-size and minimum font-size for given font-size\n $fs-diff: $fs - $fs-min;\n\n // Base font-size formatting\n // No need to check if the unit is valid, because we did that before\n $min-width: if($rfs-font-size-unit == rem, #{$fs-min / $rfs-rem-value}rem, #{$fs-min}px);\n\n // If two-dimensional, use smallest of screen width and height\n $variable-unit: if($rfs-two-dimensional, vmin, vw);\n\n // Calculate the variable width between 0 and $rfs-breakpoint\n $variable-width: #{$fs-diff * 100 / $rfs-breakpoint}#{$variable-unit};\n\n // Set the calculated font-size.\n $rfs-fluid: calc(#{$min-width} + #{$variable-width}) #{$rfs-suffix};\n }\n\n // Rendering\n @if $rfs-fluid == null {\n // Only render static font-size if no fluid font-size is available\n font-size: $rfs-static;\n }\n @else {\n $mq-value: null;\n\n // RFS breakpoint formatting\n @if $rfs-breakpoint-unit == em or $rfs-breakpoint-unit == rem {\n $mq-value: #{$rfs-breakpoint / $rfs-rem-value}#{$rfs-breakpoint-unit};\n }\n @else if $rfs-breakpoint-unit == px {\n $mq-value: #{$rfs-breakpoint}px;\n }\n @else {\n @error \"`#{$rfs-breakpoint-unit}` is not a valid unit for $rfs-breakpoint-unit. Use `px`, `em` or `rem`.\";\n }\n\n @if $rfs-class == \"disable\" {\n // Adding an extra class increases specificity,\n // which prevents the media query to override the font size\n &,\n .disable-responsive-font-size &,\n &.disable-responsive-font-size {\n font-size: $rfs-static;\n }\n }\n @else {\n font-size: $rfs-static;\n }\n\n @if $rfs-two-dimensional {\n @media (max-width: #{$mq-value}), (max-height: #{$mq-value}) {\n @if $rfs-class == \"enable\" {\n .enable-responsive-font-size &,\n &.enable-responsive-font-size {\n font-size: $rfs-fluid;\n }\n }\n @else {\n font-size: $rfs-fluid;\n }\n\n @if $rfs-safari-iframe-resize-bug-fix {\n // stylelint-disable-next-line length-zero-no-unit\n min-width: 0vw;\n }\n }\n }\n @else {\n @media (max-width: #{$mq-value}) {\n @if $rfs-class == \"enable\" {\n .enable-responsive-font-size &,\n &.enable-responsive-font-size {\n font-size: $rfs-fluid;\n }\n }\n @else {\n font-size: $rfs-fluid;\n }\n\n @if $rfs-safari-iframe-resize-bug-fix {\n // stylelint-disable-next-line length-zero-no-unit\n min-width: 0vw;\n }\n }\n }\n }\n }\n}\n\n// The font-size & responsive-font-size mixin uses RFS to rescale font sizes\n@mixin font-size($fs, $important: false) {\n @include rfs($fs, $important);\n}\n\n@mixin responsive-font-size($fs, $important: false) {\n @include rfs($fs, $important);\n}\n", + "// Deprecate mixin\n//\n// This mixin can be used to deprecate mixins or functions.\n// `$enable-deprecation-messages` is a global variable, `$ignore-warning` is a variable that can be passed to\n// some deprecated mixins to suppress the warning (for example if the mixin is still be used in the current version of Bootstrap)\n@mixin deprecate($name, $deprecate-version, $remove-version, $ignore-warning: false) {\n @if ($enable-deprecation-messages != false and $ignore-warning != true) {\n @warn \"#{$name} has been deprecated as of #{$deprecate-version}. It will be removed entirely in #{$remove-version}.\";\n }\n}\n", + "// Breakpoint viewport sizes and media queries.\n//\n// Breakpoints are defined as a map of (name: minimum width), order from small to large:\n//\n// (xs: 0, sm: 576px, md: 768px, lg: 992px, xl: 1200px)\n//\n// The map defined in the `$grid-breakpoints` global variable is used as the `$breakpoints` argument by default.\n\n// Name of the next breakpoint, or null for the last breakpoint.\n//\n// >> breakpoint-next(sm)\n// md\n// >> breakpoint-next(sm, (xs: 0, sm: 576px, md: 768px, lg: 992px, xl: 1200px))\n// md\n// >> breakpoint-next(sm, $breakpoint-names: (xs sm md lg xl))\n// md\n@function breakpoint-next($name, $breakpoints: $grid-breakpoints, $breakpoint-names: map-keys($breakpoints)) {\n $n: index($breakpoint-names, $name);\n @return if($n != null and $n < length($breakpoint-names), nth($breakpoint-names, $n + 1), null);\n}\n\n// Minimum breakpoint width. Null for the smallest (first) breakpoint.\n//\n// >> breakpoint-min(sm, (xs: 0, sm: 576px, md: 768px, lg: 992px, xl: 1200px))\n// 576px\n@function breakpoint-min($name, $breakpoints: $grid-breakpoints) {\n $min: map-get($breakpoints, $name);\n @return if($min != 0, $min, null);\n}\n\n// Maximum breakpoint width. Null for the largest (last) breakpoint.\n// The maximum value is calculated as the minimum of the next one less 0.02px\n// to work around the limitations of `min-` and `max-` prefixes and viewports with fractional widths.\n// See https://www.w3.org/TR/mediaqueries-4/#mq-min-max\n// Uses 0.02px rather than 0.01px to work around a current rounding bug in Safari.\n// See https://bugs.webkit.org/show_bug.cgi?id=178261\n//\n// >> breakpoint-max(sm, (xs: 0, sm: 576px, md: 768px, lg: 992px, xl: 1200px))\n// 767.98px\n@function breakpoint-max($name, $breakpoints: $grid-breakpoints) {\n $next: breakpoint-next($name, $breakpoints);\n @return if($next, breakpoint-min($next, $breakpoints) - .02, null);\n}\n\n// Returns a blank string if smallest breakpoint, otherwise returns the name with a dash in front.\n// Useful for making responsive utilities.\n//\n// >> breakpoint-infix(xs, (xs: 0, sm: 576px, md: 768px, lg: 992px, xl: 1200px))\n// \"\" (Returns a blank string)\n// >> breakpoint-infix(sm, (xs: 0, sm: 576px, md: 768px, lg: 992px, xl: 1200px))\n// \"-sm\"\n@function breakpoint-infix($name, $breakpoints: $grid-breakpoints) {\n @return if(breakpoint-min($name, $breakpoints) == null, \"\", \"-#{$name}\");\n}\n\n// Media of at least the minimum breakpoint width. No query for the smallest breakpoint.\n// Makes the @content apply to the given breakpoint and wider.\n@mixin media-breakpoint-up($name, $breakpoints: $grid-breakpoints) {\n $min: breakpoint-min($name, $breakpoints);\n @if $min {\n @media (min-width: $min) {\n @content;\n }\n } @else {\n @content;\n }\n}\n\n// Media of at most the maximum breakpoint width. No query for the largest breakpoint.\n// Makes the @content apply to the given breakpoint and narrower.\n@mixin media-breakpoint-down($name, $breakpoints: $grid-breakpoints) {\n $max: breakpoint-max($name, $breakpoints);\n @if $max {\n @media (max-width: $max) {\n @content;\n }\n } @else {\n @content;\n }\n}\n\n// Media that spans multiple breakpoint widths.\n// Makes the @content apply between the min and max breakpoints\n@mixin media-breakpoint-between($lower, $upper, $breakpoints: $grid-breakpoints) {\n $min: breakpoint-min($lower, $breakpoints);\n $max: breakpoint-max($upper, $breakpoints);\n\n @if $min != null and $max != null {\n @media (min-width: $min) and (max-width: $max) {\n @content;\n }\n } @else if $max == null {\n @include media-breakpoint-up($lower, $breakpoints) {\n @content;\n }\n } @else if $min == null {\n @include media-breakpoint-down($upper, $breakpoints) {\n @content;\n }\n }\n}\n\n// Media between the breakpoint's minimum and maximum widths.\n// No minimum for the smallest breakpoint, and no maximum for the largest one.\n// Makes the @content apply only to the given breakpoint, not viewports any wider or narrower.\n@mixin media-breakpoint-only($name, $breakpoints: $grid-breakpoints) {\n $min: breakpoint-min($name, $breakpoints);\n $max: breakpoint-max($name, $breakpoints);\n\n @if $min != null and $max != null {\n @media (min-width: $min) and (max-width: $max) {\n @content;\n }\n } @else if $max == null {\n @include media-breakpoint-up($name, $breakpoints) {\n @content;\n }\n } @else if $min == null {\n @include media-breakpoint-down($name, $breakpoints) {\n @content;\n }\n }\n}\n", + "// Hover mixin and `$enable-hover-media-query` are deprecated.\n//\n// Originally added during our alphas and maintained during betas, this mixin was\n// designed to prevent `:hover` stickiness on iOS-an issue where hover styles\n// would persist after initial touch.\n//\n// For backward compatibility, we've kept these mixins and updated them to\n// always return their regular pseudo-classes instead of a shimmed media query.\n//\n// Issue: https://github.com/twbs/bootstrap/issues/25195\n\n@mixin hover {\n &:hover { @content; }\n}\n\n@mixin hover-focus {\n &:hover,\n &:focus {\n @content;\n }\n}\n\n@mixin plain-hover-focus {\n &,\n &:hover,\n &:focus {\n @content;\n }\n}\n\n@mixin hover-focus-active {\n &:hover,\n &:focus,\n &:active {\n @content;\n }\n}\n", + "// Image Mixins\n// - Responsive image\n// - Retina image\n\n\n// Responsive image\n//\n// Keep images from scaling beyond the width of their parents.\n\n@mixin img-fluid {\n // Part 1: Set a maximum relative to the parent\n max-width: 100%;\n // Part 2: Override the height to auto, otherwise images will be stretched\n // when setting a width and height attribute on the img element.\n height: auto;\n}\n\n\n// Retina image\n//\n// Short retina mixin for setting background-image and -size.\n\n@mixin img-retina($file-1x, $file-2x, $width-1x, $height-1x) {\n background-image: url($file-1x);\n\n // Autoprefixer takes care of adding -webkit-min-device-pixel-ratio and -o-min-device-pixel-ratio,\n // but doesn't convert dppx=>dpi.\n // There's no such thing as unprefixed min-device-pixel-ratio since it's nonstandard.\n // Compatibility info: https://caniuse.com/#feat=css-media-resolution\n @media only screen and (min-resolution: 192dpi), // IE9-11 don't support dppx\n only screen and (min-resolution: 2dppx) { // Standardized\n background-image: url($file-2x);\n background-size: $width-1x $height-1x;\n }\n @include deprecate(\"`img-retina()`\", \"v4.3.0\", \"v5\");\n}\n", + "@mixin badge-variant($bg) {\n color: color-yiq($bg);\n background-color: $bg;\n\n @at-root a#{&} {\n @include hover-focus {\n color: color-yiq($bg);\n background-color: darken($bg, 10%);\n }\n\n &:focus,\n &.focus {\n outline: 0;\n box-shadow: 0 0 0 $badge-focus-width rgba($bg, .5);\n }\n }\n}\n", + "// Resize anything\n\n@mixin resizable($direction) {\n overflow: auto; // Per CSS3 UI, `resize` only applies when `overflow` isn't `visible`\n resize: $direction; // Options: horizontal, vertical, both\n}\n", + "// Only display content to screen readers\n//\n// See: https://a11yproject.com/posts/how-to-hide-content/\n// See: https://hugogiraudel.com/2016/10/13/css-hide-and-seek/\n\n@mixin sr-only {\n position: absolute;\n width: 1px;\n height: 1px;\n padding: 0;\n overflow: hidden;\n clip: rect(0, 0, 0, 0);\n white-space: nowrap;\n border: 0;\n}\n\n// Use in conjunction with .sr-only to only display content when it's focused.\n//\n// Useful for \"Skip to main content\" links; see https://www.w3.org/TR/2013/NOTE-WCAG20-TECHS-20130905/G1\n//\n// Credit: HTML5 Boilerplate\n\n@mixin sr-only-focusable {\n &:active,\n &:focus {\n position: static;\n width: auto;\n height: auto;\n overflow: visible;\n clip: auto;\n white-space: normal;\n }\n}\n", + "// Sizing shortcuts\n\n@mixin size($width, $height: $width) {\n width: $width;\n height: $height;\n @include deprecate(\"`size()`\", \"v4.3.0\", \"v5\");\n}\n", + "@mixin reset-text {\n font-family: $font-family-base;\n // We deliberately do NOT reset font-size or word-wrap.\n font-style: normal;\n font-weight: $font-weight-normal;\n line-height: $line-height-base;\n text-align: left; // Fallback for where `start` is not supported\n text-align: start;\n text-decoration: none;\n text-shadow: none;\n text-transform: none;\n letter-spacing: normal;\n word-break: normal;\n word-spacing: normal;\n white-space: normal;\n line-break: auto;\n}\n", + "// stylelint-disable declaration-no-important\n\n// Typography\n\n@mixin text-emphasis-variant($parent, $color) {\n #{$parent} {\n color: $color !important;\n }\n @if $emphasized-link-hover-darken-percentage != 0 {\n a#{$parent} {\n @include hover-focus {\n color: darken($color, $emphasized-link-hover-darken-percentage) !important;\n }\n }\n }\n}\n", + "// CSS image replacement\n@mixin text-hide($ignore-warning: false) {\n // stylelint-disable-next-line font-family-no-missing-generic-family-keyword\n font: 0/0 a;\n color: transparent;\n text-shadow: none;\n background-color: transparent;\n border: 0;\n\n @include deprecate(\"`text-hide()`\", \"v4.1.0\", \"v5\", $ignore-warning);\n}\n", + "// Text truncate\n// Requires inline-block or block for proper styling\n\n@mixin text-truncate() {\n overflow: hidden;\n text-overflow: ellipsis;\n white-space: nowrap;\n}\n", + "// stylelint-disable declaration-no-important\n\n// Visibility\n\n@mixin invisible($visibility) {\n visibility: $visibility !important;\n @include deprecate(\"`invisible()`\", \"v4.3.0\", \"v5\");\n}\n", + "@mixin alert-variant($background, $border, $color) {\n color: $color;\n @include gradient-bg($background);\n border-color: $border;\n\n hr {\n border-top-color: darken($border, 5%);\n }\n\n .alert-link {\n color: darken($color, 10%);\n }\n}\n", + "// Button variants\n//\n// Easily pump out default styles, as well as :hover, :focus, :active,\n// and disabled options for all buttons\n\n@mixin button-variant($background, $border, $hover-background: darken($background, 7.5%), $hover-border: darken($border, 10%), $active-background: darken($background, 10%), $active-border: darken($border, 12.5%)) {\n color: color-yiq($background);\n @include gradient-bg($background);\n border-color: $border;\n @include box-shadow($btn-box-shadow);\n\n @include hover {\n color: color-yiq($hover-background);\n @include gradient-bg($hover-background);\n border-color: $hover-border;\n }\n\n &:focus,\n &.focus {\n // Avoid using mixin so we can pass custom focus shadow properly\n @if $enable-shadows {\n box-shadow: $btn-box-shadow, 0 0 0 $btn-focus-width rgba(mix(color-yiq($background), $border, 15%), .5);\n } @else {\n box-shadow: 0 0 0 $btn-focus-width rgba(mix(color-yiq($background), $border, 15%), .5);\n }\n }\n\n // Disabled comes first so active can properly restyle\n &.disabled,\n &:disabled {\n color: color-yiq($background);\n background-color: $background;\n border-color: $border;\n // Remove CSS gradients if they're enabled\n @if $enable-gradients {\n background-image: none;\n }\n }\n\n &:not(:disabled):not(.disabled):active,\n &:not(:disabled):not(.disabled).active,\n .show > &.dropdown-toggle {\n color: color-yiq($active-background);\n background-color: $active-background;\n @if $enable-gradients {\n background-image: none; // Remove the gradient for the pressed/active state\n }\n border-color: $active-border;\n\n &:focus {\n // Avoid using mixin so we can pass custom focus shadow properly\n @if $enable-shadows and $btn-active-box-shadow != none {\n box-shadow: $btn-active-box-shadow, 0 0 0 $btn-focus-width rgba(mix(color-yiq($background), $border, 15%), .5);\n } @else {\n box-shadow: 0 0 0 $btn-focus-width rgba(mix(color-yiq($background), $border, 15%), .5);\n }\n }\n }\n}\n\n@mixin button-outline-variant($color, $color-hover: color-yiq($color), $active-background: $color, $active-border: $color) {\n color: $color;\n border-color: $color;\n\n @include hover {\n color: $color-hover;\n background-color: $active-background;\n border-color: $active-border;\n }\n\n &:focus,\n &.focus {\n box-shadow: 0 0 0 $btn-focus-width rgba($color, .5);\n }\n\n &.disabled,\n &:disabled {\n color: $color;\n background-color: transparent;\n }\n\n &:not(:disabled):not(.disabled):active,\n &:not(:disabled):not(.disabled).active,\n .show > &.dropdown-toggle {\n color: color-yiq($active-background);\n background-color: $active-background;\n border-color: $active-border;\n\n &:focus {\n // Avoid using mixin so we can pass custom focus shadow properly\n @if $enable-shadows and $btn-active-box-shadow != none {\n box-shadow: $btn-active-box-shadow, 0 0 0 $btn-focus-width rgba($color, .5);\n } @else {\n box-shadow: 0 0 0 $btn-focus-width rgba($color, .5);\n }\n }\n }\n}\n\n// Button sizes\n@mixin button-size($padding-y, $padding-x, $font-size, $line-height, $border-radius) {\n padding: $padding-y $padding-x;\n @include font-size($font-size);\n line-height: $line-height;\n // Manually declare to provide an override to the browser default\n @include border-radius($border-radius, 0);\n}\n", + "@mixin caret-down {\n border-top: $caret-width solid;\n border-right: $caret-width solid transparent;\n border-bottom: 0;\n border-left: $caret-width solid transparent;\n}\n\n@mixin caret-up {\n border-top: 0;\n border-right: $caret-width solid transparent;\n border-bottom: $caret-width solid;\n border-left: $caret-width solid transparent;\n}\n\n@mixin caret-right {\n border-top: $caret-width solid transparent;\n border-right: 0;\n border-bottom: $caret-width solid transparent;\n border-left: $caret-width solid;\n}\n\n@mixin caret-left {\n border-top: $caret-width solid transparent;\n border-right: $caret-width solid;\n border-bottom: $caret-width solid transparent;\n}\n\n@mixin caret($direction: down) {\n @if $enable-caret {\n &::after {\n display: inline-block;\n margin-left: $caret-spacing;\n vertical-align: $caret-vertical-align;\n content: \"\";\n @if $direction == down {\n @include caret-down;\n } @else if $direction == up {\n @include caret-up;\n } @else if $direction == right {\n @include caret-right;\n }\n }\n\n @if $direction == left {\n &::after {\n display: none;\n }\n\n &::before {\n display: inline-block;\n margin-right: $caret-spacing;\n vertical-align: $caret-vertical-align;\n content: \"\";\n @include caret-left;\n }\n }\n\n &:empty::after {\n margin-left: 0;\n }\n }\n}\n", + "// Pagination\n\n@mixin pagination-size($padding-y, $padding-x, $font-size, $line-height, $border-radius) {\n .page-link {\n padding: $padding-y $padding-x;\n @include font-size($font-size);\n line-height: $line-height;\n }\n\n .page-item {\n &:first-child {\n .page-link {\n @include border-left-radius($border-radius);\n }\n }\n &:last-child {\n .page-link {\n @include border-right-radius($border-radius);\n }\n }\n }\n}\n", + "// Lists\n\n// Unstyled keeps list items block level, just removes default browser padding and list-style\n@mixin list-unstyled {\n padding-left: 0;\n list-style: none;\n}\n", + "// List Groups\n\n@mixin list-group-item-variant($state, $background, $color) {\n .list-group-item-#{$state} {\n color: $color;\n background-color: $background;\n\n &.list-group-item-action {\n @include hover-focus {\n color: $color;\n background-color: darken($background, 5%);\n }\n\n &.active {\n color: $white;\n background-color: $color;\n border-color: $color;\n }\n }\n }\n}\n", + "// Horizontal dividers\n//\n// Dividers (basically an hr) within dropdowns and nav lists\n\n@mixin nav-divider($color: $nav-divider-color, $margin-y: $nav-divider-margin-y) {\n height: 0;\n margin: $margin-y 0;\n overflow: hidden;\n border-top: 1px solid $color;\n}\n", + "// Form control focus state\n//\n// Generate a customized focus state and for any input with the specified color,\n// which defaults to the `$input-focus-border-color` variable.\n//\n// We highly encourage you to not customize the default value, but instead use\n// this to tweak colors on an as-needed basis. This aesthetic change is based on\n// WebKit's default styles, but applicable to a wider range of browsers. Its\n// usability and accessibility should be taken into account with any change.\n//\n// Example usage: change the default blue border and shadow to white for better\n// contrast against a dark gray background.\n@mixin form-control-focus() {\n &:focus {\n color: $input-focus-color;\n background-color: $input-focus-bg;\n border-color: $input-focus-border-color;\n outline: 0;\n // Avoid using mixin so we can pass custom focus shadow properly\n @if $enable-shadows {\n box-shadow: $input-box-shadow, $input-focus-box-shadow;\n } @else {\n box-shadow: $input-focus-box-shadow;\n }\n }\n}\n\n\n@mixin form-validation-state($state, $color, $icon) {\n .#{$state}-feedback {\n display: none;\n width: 100%;\n margin-top: $form-feedback-margin-top;\n @include font-size($form-feedback-font-size);\n color: $color;\n }\n\n .#{$state}-tooltip {\n position: absolute;\n top: 100%;\n z-index: 5;\n display: none;\n max-width: 100%; // Contain to parent when possible\n padding: $form-feedback-tooltip-padding-y $form-feedback-tooltip-padding-x;\n margin-top: .1rem;\n @include font-size($form-feedback-tooltip-font-size);\n line-height: $form-feedback-tooltip-line-height;\n color: color-yiq($color);\n background-color: rgba($color, $form-feedback-tooltip-opacity);\n @include border-radius($form-feedback-tooltip-border-radius);\n }\n\n .form-control {\n .was-validated &:#{$state},\n &.is-#{$state} {\n border-color: $color;\n\n @if $enable-validation-icons {\n padding-right: $input-height-inner;\n background-image: $icon;\n background-repeat: no-repeat;\n background-position: center right $input-height-inner-quarter;\n background-size: $input-height-inner-half $input-height-inner-half;\n }\n\n &:focus {\n border-color: $color;\n box-shadow: 0 0 0 $input-focus-width rgba($color, .25);\n }\n\n ~ .#{$state}-feedback,\n ~ .#{$state}-tooltip {\n display: block;\n }\n }\n }\n\n // stylelint-disable-next-line selector-no-qualifying-type\n textarea.form-control {\n .was-validated &:#{$state},\n &.is-#{$state} {\n @if $enable-validation-icons {\n padding-right: $input-height-inner;\n background-position: top $input-height-inner-quarter right $input-height-inner-quarter;\n }\n }\n }\n\n .custom-select {\n .was-validated &:#{$state},\n &.is-#{$state} {\n border-color: $color;\n\n @if $enable-validation-icons {\n padding-right: $custom-select-feedback-icon-padding-right;\n background: $custom-select-background, $icon $custom-select-bg no-repeat $custom-select-feedback-icon-position / $custom-select-feedback-icon-size;\n }\n\n &:focus {\n border-color: $color;\n box-shadow: 0 0 0 $input-focus-width rgba($color, .25);\n }\n\n ~ .#{$state}-feedback,\n ~ .#{$state}-tooltip {\n display: block;\n }\n }\n }\n\n\n .form-control-file {\n .was-validated &:#{$state},\n &.is-#{$state} {\n ~ .#{$state}-feedback,\n ~ .#{$state}-tooltip {\n display: block;\n }\n }\n }\n\n .form-check-input {\n .was-validated &:#{$state},\n &.is-#{$state} {\n ~ .form-check-label {\n color: $color;\n }\n\n ~ .#{$state}-feedback,\n ~ .#{$state}-tooltip {\n display: block;\n }\n }\n }\n\n .custom-control-input {\n .was-validated &:#{$state},\n &.is-#{$state} {\n ~ .custom-control-label {\n color: $color;\n\n &::before {\n border-color: $color;\n }\n }\n\n ~ .#{$state}-feedback,\n ~ .#{$state}-tooltip {\n display: block;\n }\n\n &:checked {\n ~ .custom-control-label::before {\n border-color: lighten($color, 10%);\n @include gradient-bg(lighten($color, 10%));\n }\n }\n\n &:focus {\n ~ .custom-control-label::before {\n box-shadow: 0 0 0 $input-focus-width rgba($color, .25);\n }\n\n &:not(:checked) ~ .custom-control-label::before {\n border-color: $color;\n }\n }\n }\n }\n\n // custom file\n .custom-file-input {\n .was-validated &:#{$state},\n &.is-#{$state} {\n ~ .custom-file-label {\n border-color: $color;\n }\n\n ~ .#{$state}-feedback,\n ~ .#{$state}-tooltip {\n display: block;\n }\n\n &:focus {\n ~ .custom-file-label {\n border-color: $color;\n box-shadow: 0 0 0 $input-focus-width rgba($color, .25);\n }\n }\n }\n }\n}\n", + "// Tables\n\n@mixin table-row-variant($state, $background, $border: null) {\n // Exact selectors below required to override `.table-striped` and prevent\n // inheritance to nested tables.\n .table-#{$state} {\n &,\n > th,\n > td {\n background-color: $background;\n }\n\n @if $border != null {\n th,\n td,\n thead th,\n tbody + tbody {\n border-color: $border;\n }\n }\n }\n\n // Hover states for `.table-hover`\n // Note: this is not available for cells or rows within `thead` or `tfoot`.\n .table-hover {\n $hover-background: darken($background, 5%);\n\n .table-#{$state} {\n @include hover {\n background-color: $hover-background;\n\n > td,\n > th {\n background-color: $hover-background;\n }\n }\n }\n }\n}\n", + "// stylelint-disable declaration-no-important\n\n// Contextual backgrounds\n\n@mixin bg-variant($parent, $color) {\n #{$parent} {\n background-color: $color !important;\n }\n a#{$parent},\n button#{$parent} {\n @include hover-focus {\n background-color: darken($color, 10%) !important;\n }\n }\n}\n\n@mixin bg-gradient-variant($parent, $color) {\n #{$parent} {\n background: $color linear-gradient(180deg, mix($body-bg, $color, 15%), $color) repeat-x !important;\n }\n}\n", + "// stylelint-disable property-blacklist\n// Single side border-radius\n\n@mixin border-radius($radius: $border-radius, $fallback-border-radius: false) {\n @if $enable-rounded {\n border-radius: $radius;\n }\n @else if $fallback-border-radius != false {\n border-radius: $fallback-border-radius;\n }\n}\n\n@mixin border-top-radius($radius) {\n @if $enable-rounded {\n border-top-left-radius: $radius;\n border-top-right-radius: $radius;\n }\n}\n\n@mixin border-right-radius($radius) {\n @if $enable-rounded {\n border-top-right-radius: $radius;\n border-bottom-right-radius: $radius;\n }\n}\n\n@mixin border-bottom-radius($radius) {\n @if $enable-rounded {\n border-bottom-right-radius: $radius;\n border-bottom-left-radius: $radius;\n }\n}\n\n@mixin border-left-radius($radius) {\n @if $enable-rounded {\n border-top-left-radius: $radius;\n border-bottom-left-radius: $radius;\n }\n}\n\n@mixin border-top-left-radius($radius) {\n @if $enable-rounded {\n border-top-left-radius: $radius;\n }\n}\n\n@mixin border-top-right-radius($radius) {\n @if $enable-rounded {\n border-top-right-radius: $radius;\n }\n}\n\n@mixin border-bottom-right-radius($radius) {\n @if $enable-rounded {\n border-bottom-right-radius: $radius;\n }\n}\n\n@mixin border-bottom-left-radius($radius) {\n @if $enable-rounded {\n border-bottom-left-radius: $radius;\n }\n}\n", + "@mixin box-shadow($shadow...) {\n @if $enable-shadows {\n $result: ();\n\n @if (length($shadow) == 1) {\n // We can pass `@include box-shadow(none);`\n $result: $shadow;\n } @else {\n // Filter to avoid invalid properties for example `box-shadow: none, 1px 1px black;`\n @for $i from 1 through length($shadow) {\n @if nth($shadow, $i) != \"none\" {\n $result: append($result, nth($shadow, $i), \"comma\");\n }\n }\n }\n @if (length($result) > 0) {\n box-shadow: $result;\n }\n }\n}\n", + "// Gradients\n\n@mixin gradient-bg($color) {\n @if $enable-gradients {\n background: $color linear-gradient(180deg, mix($body-bg, $color, 15%), $color) repeat-x;\n } @else {\n background-color: $color;\n }\n}\n\n// Horizontal gradient, from left to right\n//\n// Creates two color stops, start and end, by specifying a color and position for each color stop.\n@mixin gradient-x($start-color: $gray-700, $end-color: $gray-800, $start-percent: 0%, $end-percent: 100%) {\n background-image: linear-gradient(to right, $start-color $start-percent, $end-color $end-percent);\n background-repeat: repeat-x;\n}\n\n// Vertical gradient, from top to bottom\n//\n// Creates two color stops, start and end, by specifying a color and position for each color stop.\n@mixin gradient-y($start-color: $gray-700, $end-color: $gray-800, $start-percent: 0%, $end-percent: 100%) {\n background-image: linear-gradient(to bottom, $start-color $start-percent, $end-color $end-percent);\n background-repeat: repeat-x;\n}\n\n@mixin gradient-directional($start-color: $gray-700, $end-color: $gray-800, $deg: 45deg) {\n background-image: linear-gradient($deg, $start-color, $end-color);\n background-repeat: repeat-x;\n}\n@mixin gradient-x-three-colors($start-color: $blue, $mid-color: $purple, $color-stop: 50%, $end-color: $red) {\n background-image: linear-gradient(to right, $start-color, $mid-color $color-stop, $end-color);\n background-repeat: no-repeat;\n}\n@mixin gradient-y-three-colors($start-color: $blue, $mid-color: $purple, $color-stop: 50%, $end-color: $red) {\n background-image: linear-gradient($start-color, $mid-color $color-stop, $end-color);\n background-repeat: no-repeat;\n}\n@mixin gradient-radial($inner-color: $gray-700, $outer-color: $gray-800) {\n background-image: radial-gradient(circle, $inner-color, $outer-color);\n background-repeat: no-repeat;\n}\n@mixin gradient-striped($color: rgba($white, .15), $angle: 45deg) {\n background-image: linear-gradient($angle, $color 25%, transparent 25%, transparent 50%, $color 50%, $color 75%, transparent 75%, transparent);\n}\n", + "// stylelint-disable property-blacklist\n@mixin transition($transition...) {\n @if $enable-transitions {\n @if length($transition) == 0 {\n transition: $transition-base;\n } @else {\n transition: $transition;\n }\n }\n\n @if $enable-prefers-reduced-motion-media-query {\n @media (prefers-reduced-motion: reduce) {\n transition: none;\n }\n }\n}\n", + "@mixin clearfix() {\n &::after {\n display: block;\n clear: both;\n content: \"\";\n }\n}\n", + "// Framework grid generation\n//\n// Used only by Bootstrap to generate the correct number of grid classes given\n// any value of `$grid-columns`.\n\n@mixin make-grid-columns($columns: $grid-columns, $gutter: $grid-gutter-width, $breakpoints: $grid-breakpoints) {\n // Common properties for all breakpoints\n %grid-column {\n position: relative;\n width: 100%;\n padding-right: $gutter / 2;\n padding-left: $gutter / 2;\n }\n\n @each $breakpoint in map-keys($breakpoints) {\n $infix: breakpoint-infix($breakpoint, $breakpoints);\n\n // Allow columns to stretch full width below their breakpoints\n @for $i from 1 through $columns {\n .col#{$infix}-#{$i} {\n @extend %grid-column;\n }\n }\n .col#{$infix},\n .col#{$infix}-auto {\n @extend %grid-column;\n }\n\n @include media-breakpoint-up($breakpoint, $breakpoints) {\n // Provide basic `.col-{bp}` classes for equal-width flexbox columns\n .col#{$infix} {\n flex-basis: 0;\n flex-grow: 1;\n max-width: 100%;\n }\n .col#{$infix}-auto {\n flex: 0 0 auto;\n width: auto;\n max-width: 100%; // Reset earlier grid tiers\n }\n\n @for $i from 1 through $columns {\n .col#{$infix}-#{$i} {\n @include make-col($i, $columns);\n }\n }\n\n .order#{$infix}-first { order: -1; }\n\n .order#{$infix}-last { order: $columns + 1; }\n\n @for $i from 0 through $columns {\n .order#{$infix}-#{$i} { order: $i; }\n }\n\n // `$columns - 1` because offsetting by the width of an entire row isn't possible\n @for $i from 0 through ($columns - 1) {\n @if not ($infix == \"\" and $i == 0) { // Avoid emitting useless .offset-0\n .offset#{$infix}-#{$i} {\n @include make-col-offset($i, $columns);\n }\n }\n }\n }\n }\n}\n", + "/// Grid system\n//\n// Generate semantic grid columns with these mixins.\n\n@mixin make-container($gutter: $grid-gutter-width) {\n width: 100%;\n padding-right: $gutter / 2;\n padding-left: $gutter / 2;\n margin-right: auto;\n margin-left: auto;\n}\n\n\n// For each breakpoint, define the maximum width of the container in a media query\n@mixin make-container-max-widths($max-widths: $container-max-widths, $breakpoints: $grid-breakpoints) {\n @each $breakpoint, $container-max-width in $max-widths {\n @include media-breakpoint-up($breakpoint, $breakpoints) {\n max-width: $container-max-width;\n }\n }\n}\n\n@mixin make-row($gutter: $grid-gutter-width) {\n display: flex;\n flex-wrap: wrap;\n margin-right: -$gutter / 2;\n margin-left: -$gutter / 2;\n}\n\n@mixin make-col-ready($gutter: $grid-gutter-width) {\n position: relative;\n // Prevent columns from becoming too narrow when at smaller grid tiers by\n // always setting `width: 100%;`. This works because we use `flex` values\n // later on to override this initial width.\n width: 100%;\n padding-right: $gutter / 2;\n padding-left: $gutter / 2;\n}\n\n@mixin make-col($size, $columns: $grid-columns) {\n flex: 0 0 percentage($size / $columns);\n // Add a `max-width` to ensure content within each column does not blow out\n // the width of the column. Applies to IE10+ and Firefox. Chrome and Safari\n // do not appear to require this.\n max-width: percentage($size / $columns);\n}\n\n@mixin make-col-offset($size, $columns: $grid-columns) {\n $num: $size / $columns;\n margin-left: if($num == 0, 0, percentage($num));\n}\n", + "// stylelint-disable declaration-no-important\n\n@mixin float-left {\n float: left !important;\n @include deprecate(\"The `float-left` mixin\", \"v4.3.0\", \"v5\");\n}\n@mixin float-right {\n float: right !important;\n @include deprecate(\"The `float-right` mixin\", \"v4.3.0\", \"v5\");\n}\n@mixin float-none {\n float: none !important;\n @include deprecate(\"The `float-none` mixin\", \"v4.3.0\", \"v5\");\n}\n", + ":root {\n // Custom variable values only support SassScript inside `#{}`.\n @each $color, $value in $colors {\n --#{$color}: #{$value};\n }\n\n @each $color, $value in $theme-colors {\n --#{$color}: #{$value};\n }\n\n @each $bp, $value in $grid-breakpoints {\n --breakpoint-#{$bp}: #{$value};\n }\n\n // Use `inspect` for lists so that quoted items keep the quotes.\n // See https://github.com/sass/sass/issues/2383#issuecomment-336349172\n --font-family-sans-serif: #{inspect($font-family-sans-serif)};\n --font-family-monospace: #{inspect($font-family-monospace)};\n}\n", + "// stylelint-disable at-rule-no-vendor-prefix, declaration-no-important, selector-no-qualifying-type, property-no-vendor-prefix\n\n// Reboot\n//\n// Normalization of HTML elements, manually forked from Normalize.css to remove\n// styles targeting irrelevant browsers while applying new styles.\n//\n// Normalize is licensed MIT. https://github.com/necolas/normalize.css\n\n\n// Document\n//\n// 1. Change from `box-sizing: content-box` so that `width` is not affected by `padding` or `border`.\n// 2. Change the default font family in all browsers.\n// 3. Correct the line height in all browsers.\n// 4. Prevent adjustments of font size after orientation changes in IE on Windows Phone and in iOS.\n// 5. Change the default tap highlight to be completely transparent in iOS.\n\n*,\n*::before,\n*::after {\n box-sizing: border-box; // 1\n}\n\nhtml {\n font-family: sans-serif; // 2\n line-height: 1.15; // 3\n -webkit-text-size-adjust: 100%; // 4\n -webkit-tap-highlight-color: rgba($black, 0); // 5\n}\n\n// Shim for \"new\" HTML5 structural elements to display correctly (IE10, older browsers)\n// TODO: remove in v5\n// stylelint-disable-next-line selector-list-comma-newline-after\narticle, aside, figcaption, figure, footer, header, hgroup, main, nav, section {\n display: block;\n}\n\n// Body\n//\n// 1. Remove the margin in all browsers.\n// 2. As a best practice, apply a default `background-color`.\n// 3. Set an explicit initial text-align value so that we can later use\n// the `inherit` value on things like `` elements.\n\nbody {\n margin: 0; // 1\n font-family: $font-family-base;\n @include font-size($font-size-base);\n font-weight: $font-weight-base;\n line-height: $line-height-base;\n color: $body-color;\n text-align: left; // 3\n background-color: $body-bg; // 2\n}\n\n// Suppress the focus outline on elements that cannot be accessed via keyboard.\n// This prevents an unwanted focus outline from appearing around elements that\n// might still respond to pointer events.\n//\n// Credit: https://github.com/suitcss/base\n[tabindex=\"-1\"]:focus {\n outline: 0 !important;\n}\n\n\n// Content grouping\n//\n// 1. Add the correct box sizing in Firefox.\n// 2. Show the overflow in Edge and IE.\n\nhr {\n box-sizing: content-box; // 1\n height: 0; // 1\n overflow: visible; // 2\n}\n\n\n//\n// Typography\n//\n\n// Remove top margins from headings\n//\n// By default, `

    `-`

    ` all receive top and bottom margins. We nuke the top\n// margin for easier control within type scales as it avoids margin collapsing.\n// stylelint-disable-next-line selector-list-comma-newline-after\nh1, h2, h3, h4, h5, h6 {\n margin-top: 0;\n margin-bottom: $headings-margin-bottom;\n}\n\n// Reset margins on paragraphs\n//\n// Similarly, the top margin on `

    `s get reset. However, we also reset the\n// bottom margin to use `rem` units instead of `em`.\np {\n margin-top: 0;\n margin-bottom: $paragraph-margin-bottom;\n}\n\n// Abbreviations\n//\n// 1. Duplicate behavior to the data-* attribute for our tooltip plugin\n// 2. Add the correct text decoration in Chrome, Edge, IE, Opera, and Safari.\n// 3. Add explicit cursor to indicate changed behavior.\n// 4. Remove the bottom border in Firefox 39-.\n// 5. Prevent the text-decoration to be skipped.\n\nabbr[title],\nabbr[data-original-title] { // 1\n text-decoration: underline; // 2\n text-decoration: underline dotted; // 2\n cursor: help; // 3\n border-bottom: 0; // 4\n text-decoration-skip-ink: none; // 5\n}\n\naddress {\n margin-bottom: 1rem;\n font-style: normal;\n line-height: inherit;\n}\n\nol,\nul,\ndl {\n margin-top: 0;\n margin-bottom: 1rem;\n}\n\nol ol,\nul ul,\nol ul,\nul ol {\n margin-bottom: 0;\n}\n\ndt {\n font-weight: $dt-font-weight;\n}\n\ndd {\n margin-bottom: .5rem;\n margin-left: 0; // Undo browser default\n}\n\nblockquote {\n margin: 0 0 1rem;\n}\n\nb,\nstrong {\n font-weight: $font-weight-bolder; // Add the correct font weight in Chrome, Edge, and Safari\n}\n\nsmall {\n @include font-size(80%); // Add the correct font size in all browsers\n}\n\n//\n// Prevent `sub` and `sup` elements from affecting the line height in\n// all browsers.\n//\n\nsub,\nsup {\n position: relative;\n @include font-size(75%);\n line-height: 0;\n vertical-align: baseline;\n}\n\nsub { bottom: -.25em; }\nsup { top: -.5em; }\n\n\n//\n// Links\n//\n\na {\n color: $link-color;\n text-decoration: $link-decoration;\n background-color: transparent; // Remove the gray background on active links in IE 10.\n\n @include hover {\n color: $link-hover-color;\n text-decoration: $link-hover-decoration;\n }\n}\n\n// And undo these styles for placeholder links/named anchors (without href)\n// which have not been made explicitly keyboard-focusable (without tabindex).\n// It would be more straightforward to just use a[href] in previous block, but that\n// causes specificity issues in many other styles that are too complex to fix.\n// See https://github.com/twbs/bootstrap/issues/19402\n\na:not([href]):not([tabindex]) {\n color: inherit;\n text-decoration: none;\n\n @include hover-focus {\n color: inherit;\n text-decoration: none;\n }\n\n &:focus {\n outline: 0;\n }\n}\n\n\n//\n// Code\n//\n\npre,\ncode,\nkbd,\nsamp {\n font-family: $font-family-monospace;\n @include font-size(1em); // Correct the odd `em` font sizing in all browsers.\n}\n\npre {\n // Remove browser default top margin\n margin-top: 0;\n // Reset browser default of `1em` to use `rem`s\n margin-bottom: 1rem;\n // Don't allow content to break outside\n overflow: auto;\n}\n\n\n//\n// Figures\n//\n\nfigure {\n // Apply a consistent margin strategy (matches our type styles).\n margin: 0 0 1rem;\n}\n\n\n//\n// Images and content\n//\n\nimg {\n vertical-align: middle;\n border-style: none; // Remove the border on images inside links in IE 10-.\n}\n\nsvg {\n // Workaround for the SVG overflow bug in IE10/11 is still required.\n // See https://github.com/twbs/bootstrap/issues/26878\n overflow: hidden;\n vertical-align: middle;\n}\n\n\n//\n// Tables\n//\n\ntable {\n border-collapse: collapse; // Prevent double borders\n}\n\ncaption {\n padding-top: $table-cell-padding;\n padding-bottom: $table-cell-padding;\n color: $table-caption-color;\n text-align: left;\n caption-side: bottom;\n}\n\nth {\n // Matches default `` alignment by inheriting from the ``, or the\n // closest parent with a set `text-align`.\n text-align: inherit;\n}\n\n\n//\n// Forms\n//\n\nlabel {\n // Allow labels to use `margin` for spacing.\n display: inline-block;\n margin-bottom: $label-margin-bottom;\n}\n\n// Remove the default `border-radius` that macOS Chrome adds.\n//\n// Details at https://github.com/twbs/bootstrap/issues/24093\nbutton {\n // stylelint-disable-next-line property-blacklist\n border-radius: 0;\n}\n\n// Work around a Firefox/IE bug where the transparent `button` background\n// results in a loss of the default `button` focus styles.\n//\n// Credit: https://github.com/suitcss/base/\nbutton:focus {\n outline: 1px dotted;\n outline: 5px auto -webkit-focus-ring-color;\n}\n\ninput,\nbutton,\nselect,\noptgroup,\ntextarea {\n margin: 0; // Remove the margin in Firefox and Safari\n font-family: inherit;\n @include font-size(inherit);\n line-height: inherit;\n}\n\nbutton,\ninput {\n overflow: visible; // Show the overflow in Edge\n}\n\nbutton,\nselect {\n text-transform: none; // Remove the inheritance of text transform in Firefox\n}\n\n// Remove the inheritance of word-wrap in Safari.\n//\n// Details at https://github.com/twbs/bootstrap/issues/24990\nselect {\n word-wrap: normal;\n}\n\n\n// 1. Prevent a WebKit bug where (2) destroys native `audio` and `video`\n// controls in Android 4.\n// 2. Correct the inability to style clickable types in iOS and Safari.\nbutton,\n[type=\"button\"], // 1\n[type=\"reset\"],\n[type=\"submit\"] {\n -webkit-appearance: button; // 2\n}\n\n// Opinionated: add \"hand\" cursor to non-disabled button elements.\n@if $enable-pointer-cursor-for-buttons {\n button,\n [type=\"button\"],\n [type=\"reset\"],\n [type=\"submit\"] {\n &:not(:disabled) {\n cursor: pointer;\n }\n }\n}\n\n// Remove inner border and padding from Firefox, but don't restore the outline like Normalize.\nbutton::-moz-focus-inner,\n[type=\"button\"]::-moz-focus-inner,\n[type=\"reset\"]::-moz-focus-inner,\n[type=\"submit\"]::-moz-focus-inner {\n padding: 0;\n border-style: none;\n}\n\ninput[type=\"radio\"],\ninput[type=\"checkbox\"] {\n box-sizing: border-box; // 1. Add the correct box sizing in IE 10-\n padding: 0; // 2. Remove the padding in IE 10-\n}\n\n\ninput[type=\"date\"],\ninput[type=\"time\"],\ninput[type=\"datetime-local\"],\ninput[type=\"month\"] {\n // Remove the default appearance of temporal inputs to avoid a Mobile Safari\n // bug where setting a custom line-height prevents text from being vertically\n // centered within the input.\n // See https://bugs.webkit.org/show_bug.cgi?id=139848\n // and https://github.com/twbs/bootstrap/issues/11266\n -webkit-appearance: listbox;\n}\n\ntextarea {\n overflow: auto; // Remove the default vertical scrollbar in IE.\n // Textareas should really only resize vertically so they don't break their (horizontal) containers.\n resize: vertical;\n}\n\nfieldset {\n // Browsers set a default `min-width: min-content;` on fieldsets,\n // unlike e.g. `

    `s, which have `min-width: 0;` by default.\n // So we reset that to ensure fieldsets behave more like a standard block element.\n // See https://github.com/twbs/bootstrap/issues/12359\n // and https://html.spec.whatwg.org/multipage/#the-fieldset-and-legend-elements\n min-width: 0;\n // Reset the default outline behavior of fieldsets so they don't affect page layout.\n padding: 0;\n margin: 0;\n border: 0;\n}\n\n// 1. Correct the text wrapping in Edge and IE.\n// 2. Correct the color inheritance from `fieldset` elements in IE.\nlegend {\n display: block;\n width: 100%;\n max-width: 100%; // 1\n padding: 0;\n margin-bottom: .5rem;\n @include font-size(1.5rem);\n line-height: inherit;\n color: inherit; // 2\n white-space: normal; // 1\n}\n\nprogress {\n vertical-align: baseline; // Add the correct vertical alignment in Chrome, Firefox, and Opera.\n}\n\n// Correct the cursor style of increment and decrement buttons in Chrome.\n[type=\"number\"]::-webkit-inner-spin-button,\n[type=\"number\"]::-webkit-outer-spin-button {\n height: auto;\n}\n\n[type=\"search\"] {\n // This overrides the extra rounded corners on search inputs in iOS so that our\n // `.form-control` class can properly style them. Note that this cannot simply\n // be added to `.form-control` as it's not specific enough. For details, see\n // https://github.com/twbs/bootstrap/issues/11586.\n outline-offset: -2px; // 2. Correct the outline style in Safari.\n -webkit-appearance: none;\n}\n\n//\n// Remove the inner padding in Chrome and Safari on macOS.\n//\n\n[type=\"search\"]::-webkit-search-decoration {\n -webkit-appearance: none;\n}\n\n//\n// 1. Correct the inability to style clickable types in iOS and Safari.\n// 2. Change font properties to `inherit` in Safari.\n//\n\n::-webkit-file-upload-button {\n font: inherit; // 2\n -webkit-appearance: button; // 1\n}\n\n//\n// Correct element displays\n//\n\noutput {\n display: inline-block;\n}\n\nsummary {\n display: list-item; // Add the correct display in all browsers\n cursor: pointer;\n}\n\ntemplate {\n display: none; // Add the correct display in IE\n}\n\n// Always hide an element with the `hidden` HTML attribute (from PureCSS).\n// Needed for proper display in IE 10-.\n[hidden] {\n display: none !important;\n}\n", + "// stylelint-disable declaration-no-important, selector-list-comma-newline-after\n\n//\n// Headings\n//\n\nh1, h2, h3, h4, h5, h6,\n.h1, .h2, .h3, .h4, .h5, .h6 {\n margin-bottom: $headings-margin-bottom;\n font-family: $headings-font-family;\n font-weight: $headings-font-weight;\n line-height: $headings-line-height;\n color: $headings-color;\n}\n\nh1, .h1 { @include font-size($h1-font-size); }\nh2, .h2 { @include font-size($h2-font-size); }\nh3, .h3 { @include font-size($h3-font-size); }\nh4, .h4 { @include font-size($h4-font-size); }\nh5, .h5 { @include font-size($h5-font-size); }\nh6, .h6 { @include font-size($h6-font-size); }\n\n.lead {\n @include font-size($lead-font-size);\n font-weight: $lead-font-weight;\n}\n\n// Type display classes\n.display-1 {\n @include font-size($display1-size);\n font-weight: $display1-weight;\n line-height: $display-line-height;\n}\n.display-2 {\n @include font-size($display2-size);\n font-weight: $display2-weight;\n line-height: $display-line-height;\n}\n.display-3 {\n @include font-size($display3-size);\n font-weight: $display3-weight;\n line-height: $display-line-height;\n}\n.display-4 {\n @include font-size($display4-size);\n font-weight: $display4-weight;\n line-height: $display-line-height;\n}\n\n\n//\n// Horizontal rules\n//\n\nhr {\n margin-top: $hr-margin-y;\n margin-bottom: $hr-margin-y;\n border: 0;\n border-top: $hr-border-width solid $hr-border-color;\n}\n\n\n//\n// Emphasis\n//\n\nsmall,\n.small {\n @include font-size($small-font-size);\n font-weight: $font-weight-normal;\n}\n\nmark,\n.mark {\n padding: $mark-padding;\n background-color: $mark-bg;\n}\n\n\n//\n// Lists\n//\n\n.list-unstyled {\n @include list-unstyled;\n}\n\n// Inline turns list items into inline-block\n.list-inline {\n @include list-unstyled;\n}\n.list-inline-item {\n display: inline-block;\n\n &:not(:last-child) {\n margin-right: $list-inline-padding;\n }\n}\n\n\n//\n// Misc\n//\n\n// Builds on `abbr`\n.initialism {\n @include font-size(90%);\n text-transform: uppercase;\n}\n\n// Blockquotes\n.blockquote {\n margin-bottom: $spacer;\n @include font-size($blockquote-font-size);\n}\n\n.blockquote-footer {\n display: block;\n @include font-size($blockquote-small-font-size);\n color: $blockquote-small-color;\n\n &::before {\n content: \"\\2014\\00A0\"; // em dash, nbsp\n }\n}\n", + "// Responsive images (ensure images don't scale beyond their parents)\n//\n// This is purposefully opt-in via an explicit class rather than being the default for all ``s.\n// We previously tried the \"images are responsive by default\" approach in Bootstrap v2,\n// and abandoned it in Bootstrap v3 because it breaks lots of third-party widgets (including Google Maps)\n// which weren't expecting the images within themselves to be involuntarily resized.\n// See also https://github.com/twbs/bootstrap/issues/18178\n.img-fluid {\n @include img-fluid;\n}\n\n\n// Image thumbnails\n.img-thumbnail {\n padding: $thumbnail-padding;\n background-color: $thumbnail-bg;\n border: $thumbnail-border-width solid $thumbnail-border-color;\n @include border-radius($thumbnail-border-radius);\n @include box-shadow($thumbnail-box-shadow);\n\n // Keep them at most 100% wide\n @include img-fluid;\n}\n\n//\n// Figures\n//\n\n.figure {\n // Ensures the caption's text aligns with the image.\n display: inline-block;\n}\n\n.figure-img {\n margin-bottom: $spacer / 2;\n line-height: 1;\n}\n\n.figure-caption {\n @include font-size($figure-caption-font-size);\n color: $figure-caption-color;\n}\n", + "// Inline code\ncode {\n @include font-size($code-font-size);\n color: $code-color;\n word-break: break-word;\n\n // Streamline the style when inside anchors to avoid broken underline and more\n a > & {\n color: inherit;\n }\n}\n\n// User input typically entered via keyboard\nkbd {\n padding: $kbd-padding-y $kbd-padding-x;\n @include font-size($kbd-font-size);\n color: $kbd-color;\n background-color: $kbd-bg;\n @include border-radius($border-radius-sm);\n @include box-shadow($kbd-box-shadow);\n\n kbd {\n padding: 0;\n @include font-size(100%);\n font-weight: $nested-kbd-font-weight;\n @include box-shadow(none);\n }\n}\n\n// Blocks of code\npre {\n display: block;\n @include font-size($code-font-size);\n color: $pre-color;\n\n // Account for some code outputs that place code tags in pre tags\n code {\n @include font-size(inherit);\n color: inherit;\n word-break: normal;\n }\n}\n\n// Enable scrollable blocks of code\n.pre-scrollable {\n max-height: $pre-scrollable-max-height;\n overflow-y: scroll;\n}\n", + "// Container widths\n//\n// Set the container width, and override it for fixed navbars in media queries.\n\n@if $enable-grid-classes {\n .container {\n @include make-container();\n @include make-container-max-widths();\n }\n}\n\n// Fluid container\n//\n// Utilizes the mixin meant for fixed width containers, but with 100% width for\n// fluid, full width layouts.\n\n@if $enable-grid-classes {\n .container-fluid {\n @include make-container();\n }\n}\n\n// Row\n//\n// Rows contain and clear the floats of your columns.\n\n@if $enable-grid-classes {\n .row {\n @include make-row();\n }\n\n // Remove the negative margin from default .row, then the horizontal padding\n // from all immediate children columns (to prevent runaway style inheritance).\n .no-gutters {\n margin-right: 0;\n margin-left: 0;\n\n > .col,\n > [class*=\"col-\"] {\n padding-right: 0;\n padding-left: 0;\n }\n }\n}\n\n// Columns\n//\n// Common styles for small and large grid columns\n\n@if $enable-grid-classes {\n @include make-grid-columns();\n}\n", + "//\n// Basic Bootstrap table\n//\n\n.table {\n width: 100%;\n margin-bottom: $spacer;\n color: $table-color;\n background-color: $table-bg; // Reset for nesting within parents with `background-color`.\n\n th,\n td {\n padding: $table-cell-padding;\n vertical-align: top;\n border-top: $table-border-width solid $table-border-color;\n }\n\n thead th {\n vertical-align: bottom;\n border-bottom: (2 * $table-border-width) solid $table-border-color;\n }\n\n tbody + tbody {\n border-top: (2 * $table-border-width) solid $table-border-color;\n }\n}\n\n\n//\n// Condensed table w/ half padding\n//\n\n.table-sm {\n th,\n td {\n padding: $table-cell-padding-sm;\n }\n}\n\n\n// Border versions\n//\n// Add or remove borders all around the table and between all the columns.\n\n.table-bordered {\n border: $table-border-width solid $table-border-color;\n\n th,\n td {\n border: $table-border-width solid $table-border-color;\n }\n\n thead {\n th,\n td {\n border-bottom-width: 2 * $table-border-width;\n }\n }\n}\n\n.table-borderless {\n th,\n td,\n thead th,\n tbody + tbody {\n border: 0;\n }\n}\n\n// Zebra-striping\n//\n// Default zebra-stripe styles (alternating gray and transparent backgrounds)\n\n.table-striped {\n tbody tr:nth-of-type(#{$table-striped-order}) {\n background-color: $table-accent-bg;\n }\n}\n\n\n// Hover effect\n//\n// Placed here since it has to come after the potential zebra striping\n\n.table-hover {\n tbody tr {\n @include hover {\n color: $table-hover-color;\n background-color: $table-hover-bg;\n }\n }\n}\n\n\n// Table backgrounds\n//\n// Exact selectors below required to override `.table-striped` and prevent\n// inheritance to nested tables.\n\n@each $color, $value in $theme-colors {\n @include table-row-variant($color, theme-color-level($color, $table-bg-level), theme-color-level($color, $table-border-level));\n}\n\n@include table-row-variant(active, $table-active-bg);\n\n\n// Dark styles\n//\n// Same table markup, but inverted color scheme: dark background and light text.\n\n// stylelint-disable-next-line no-duplicate-selectors\n.table {\n .thead-dark {\n th {\n color: $table-dark-color;\n background-color: $table-dark-bg;\n border-color: $table-dark-border-color;\n }\n }\n\n .thead-light {\n th {\n color: $table-head-color;\n background-color: $table-head-bg;\n border-color: $table-border-color;\n }\n }\n}\n\n.table-dark {\n color: $table-dark-color;\n background-color: $table-dark-bg;\n\n th,\n td,\n thead th {\n border-color: $table-dark-border-color;\n }\n\n &.table-bordered {\n border: 0;\n }\n\n &.table-striped {\n tbody tr:nth-of-type(odd) {\n background-color: $table-dark-accent-bg;\n }\n }\n\n &.table-hover {\n tbody tr {\n @include hover {\n color: $table-dark-hover-color;\n background-color: $table-dark-hover-bg;\n }\n }\n }\n}\n\n\n// Responsive tables\n//\n// Generate series of `.table-responsive-*` classes for configuring the screen\n// size of where your table will overflow.\n\n.table-responsive {\n @each $breakpoint in map-keys($grid-breakpoints) {\n $next: breakpoint-next($breakpoint, $grid-breakpoints);\n $infix: breakpoint-infix($next, $grid-breakpoints);\n\n &#{$infix} {\n @include media-breakpoint-down($breakpoint) {\n display: block;\n width: 100%;\n overflow-x: auto;\n -webkit-overflow-scrolling: touch;\n\n // Prevent double border on horizontal scroll due to use of `display: block;`\n > .table-bordered {\n border: 0;\n }\n }\n }\n }\n}\n", + "// stylelint-disable selector-no-qualifying-type\n\n//\n// Textual form controls\n//\n\n.form-control {\n display: block;\n width: 100%;\n height: $input-height;\n padding: $input-padding-y $input-padding-x;\n font-family: $input-font-family;\n @include font-size($input-font-size);\n font-weight: $input-font-weight;\n line-height: $input-line-height;\n color: $input-color;\n background-color: $input-bg;\n background-clip: padding-box;\n border: $input-border-width solid $input-border-color;\n\n // Note: This has no effect on `s in CSS.\n @include border-radius($input-border-radius, 0);\n\n @include box-shadow($input-box-shadow);\n @include transition($input-transition);\n\n // Unstyle the caret on ` receives focus\n // in IE and (under certain conditions) Edge, as it looks bad and cannot be made to\n // match the appearance of the native widget.\n // See https://github.com/twbs/bootstrap/issues/19398.\n color: $input-color;\n background-color: $input-bg;\n }\n}\n\n// Make file inputs better match text inputs by forcing them to new lines.\n.form-control-file,\n.form-control-range {\n display: block;\n width: 100%;\n}\n\n\n//\n// Labels\n//\n\n// For use with horizontal and inline forms, when you need the label (or legend)\n// text to align with the form controls.\n.col-form-label {\n padding-top: calc(#{$input-padding-y} + #{$input-border-width});\n padding-bottom: calc(#{$input-padding-y} + #{$input-border-width});\n margin-bottom: 0; // Override the `