Skip to content

@pulp-platform pulp-platform

Change the repository type filter

All

    Repositories list

    326 repositories

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •111•137•18•6•Updated Jul 4, 2026Jul 4, 2026

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •3•5•4•7•Updated Jul 4, 2026Jul 4, 2026

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •201•764•6•1•Updated Jul 3, 2026Jul 3, 2026

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •23•8•1•5•Updated Jul 3, 2026Jul 3, 2026

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •58•223•9•12•Updated Jul 3, 2026Jul 3, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •360•1.6k•50•22•Updated Jul 3, 2026Jul 3, 2026

    • pulp-actions

      Public
      Python
      •
      Apache License 2.0
      •6•11•1•3•Updated Jul 3, 2026Jul 3, 2026

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •10•21•0•6•Updated Jul 3, 2026Jul 3, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •62•379•28•10•Updated Jul 3, 2026Jul 3, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •164•22•0•8•Updated Jul 3, 2026Jul 3, 2026

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •8•5•1•9•Updated Jul 3, 2026Jul 3, 2026

    • axi_riscv_atomics

      Public
      AXI Adapter(s) for RISC-V Atomic Operations
      SystemVerilog
      •
      Other
      •23•66•1•5•Updated Jul 3, 2026Jul 3, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •113•351•23•29•Updated Jul 3, 2026Jul 3, 2026

    • magia-sdk

      Public
      C
      •
      Apache License 2.0
      •11•6•5•10•Updated Jul 2, 2026Jul 2, 2026

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •26•35•4•9•Updated Jul 2, 2026Jul 2, 2026

    • dram_rtl_sim

      Public
      SystemVerilog
      •
      Other
      •11•19•1•1•Updated Jul 2, 2026Jul 2, 2026

    • register_interface

      Public
      Generic Register Interface (contains various adapters)
      SystemVerilog
      •
      Other
      •36•140•4•6•Updated Jul 2, 2026Jul 2, 2026

    • apb

      Public
      APB Logic
      SystemVerilog
      •
      Other
      •21•26•2•5•Updated Jul 2, 2026Jul 2, 2026

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      riscvdebug
      riscvdebug
      SystemVerilog
      •
      Other
      •97•314•35•8•Updated Jul 2, 2026Jul 2, 2026

    • axi_rt

      Public
      SystemVerilog
      •
      Other
      •6•4•9•3•Updated Jul 2, 2026Jul 2, 2026

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is a…
      casicfpga
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •33•127•16•7•Updated Jul 2, 2026Jul 2, 2026

    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •61•321•3•4•Updated Jul 2, 2026Jul 2, 2026

    • pulp-linux

      Public
      Build GNU/Linux for various PULP/Cheshire-based systems.
      C
      •1•4•4•0•Updated Jul 2, 2026Jul 2, 2026

    • softhier-sdk

      Public
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Jul 1, 2026Jul 1, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •48•162•5•9•Updated Jul 1, 2026Jul 1, 2026

    • llvm-project

      Public
      C++
      •18k•15•7•2•Updated Jul 1, 2026Jul 1, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •7•23•19•1•Updated Jul 1, 2026Jul 1, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •66•315•24•5•Updated Jul 1, 2026Jul 1, 2026

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •26•21•3•4•Updated Jun 30, 2026Jun 30, 2026

    • spatz_vpu

      Public
      Spatz vector processing unit
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Jun 30, 2026Jun 30, 2026
    ProTip! When viewing an organization's repositories, you can use the props. filter to filter by custom property.